The Design Of Low-Power Memory

With the rapid development of integrated circuit process and the continuous improvement of integration, the power consumption by more and more attention. The main source of power consumption in traditional CMOS circuits is dynamic power and static power consumption. Adiabatic circuits recycle the energy of integrated circuit, which can effectively reduce the dynamic power consumption. As process geometries continue to decrease, in the deep sub-micron process, the static power consumption generated by the leakage current in the total proportion is growing. This paper selects memory as the research object, which is an important component in digital system, to design low-power memory both in dynamic power consumption and static power consumption aspects.For the dynamic power consumption in the memory circuit, the first to use single-phase adiabatic CAL (Clocked Adiabatic Logic) circuit to design SRAM (Static Random Access Memory) and CAM (Content Addressable Memory) circuit, for comparison, the structure of traditional CMOS SRAM and CAM also be designed. By HSPICE simulation results show that single-phase adiabatic CAL logic circuit can effectively reduce power consumption of the SRAM and CAM circuit. Then to draw layout of SRAM circuit in the TSMC 0.18um process, from the layout level circuit to verification the single-phase adiabatic CAL SRAM low-power effect.The static power consumption of single-phase SRAM circuit is the focus research in this paper. For CAL SRAM circuit leakage power consumption in sleep time, the first to application multi-threshold technology in power-gating switch circuit, design the power-gating multi-threshold switch to reduce the leakage power of CAL SRAM peripheral circuits, then designed to reduce the CAL SRAM cell circuit leakage power consumption in sleep time by applied drowsy cache technology. For CAL SRAM circuit when the runtime, we use dual-threshold technology and gate-length biasing technology to reduce this part leakage power consumption. The SRAM circuits that used leakage power reduction techniques all have been simulated by HSPICE, the simulation results show that the designed circuits have good effect to reduce the SRAM leakage power circuit.Near threshold technique can be applied in the circuits that have low performance and frequency to substantial reduction the power consumption in these circuits. This paper applied near threshold technology in SRAM circuit, and to identify the maximum frequency and minimum energy delay product in different voltage.