.65 Nm Td-scdma Chip Low-power Back-end Implementation

As the thrinking of the semiconductor's feature size in recent years, the integration and the speed of an IC increasing rapidly. These also introduce the power consumption problem. In deep sub micro design, timing and area optimization are not enough for IC designers' target, power issues should be taken into account immediately. Because of the IC companies face the requirement of cost and time-to-market, a power reduction technology must be introduced to the flow.This paper has studied the sources of the CMOS circuit power consumption and the method for power reduction in each design level. Expatiate some low power method in IC backend design flow with the Synopsys Design Compiler and IC Compiler, mainly descript gating clock insertion, multi-threshold voltage synthesis, Design Compiler Topography flow and power gating method in IC Compiler. Because our current flow emphasize on the timing and area optimization, the power reduction technology makes the flow mature and optimized.