The Research And Physical Design Of Low Power Technology Based On H.265 Chip

Benefiting from the continuous innovations in advanced semiconductor processes and well-designed electronic design automation tools,today's digital integrated circuits are moving toward high complexity,high performance,and high integration,but the design concept based on the compromise between performance,power consumption and area is still applicable.System-on-a-chip(So C)and system-in-package(SIP)chips are becoming mainstream in the high-end application market to meet people's demand for timely processing of massive information.In recent years,the new semiconductor driving force represented by mobile,Internet of Things,big data,5G,etc.,has strict requirements for high-performance,low-power,and miniaturized digital integrated circuit products.At present,the problem of power consumption is still outstanding.Energy saving and consumption reduction are long-term issues that design engineers must face in order to improve chip reliability,extend chip life,and reduce chip testing and heat dissipation costs.This paper takes a new generation of high-efficiency video coding standard(H.265/HEVC)chip as the research object.H.265 has high efficiency image compression and high quality compression performance,and is widely used in digital video services such as mobile wireless video and high definition video broadcasting.It has strong practicability.This article focuses on low-power technologies and discusses the importance of low-power consumption and design methods to effectively reduce power consumption.Firstly,according to the basic principles of semiconductor physics,the dynamic power and static power sources of CMOS integrated circuits are analyzed,and the methods and advantages of reducing power consumption from multiple levels are discussed.Some common low-power technologies are still the key to reducing power consumption today,such as multi-threshold voltage technology,multi-voltage technology,clock gating technology and power gating technology.How to achieve the above common technologies is the focus of this article.Secondly,based on the physical synthesis strategy of multi-threshold voltage,clock gating,multi-voltage and power gating,combined with SAED32/28 nm process library,using the industry's mainstream synthesis tool Design Compiler to complete the two-pass synthesis process from RTL code to high quality netlist.In this process,the power optimization capabilities of each synthesis strategy are compared and analyzed,and the Unified Power Format(UPF)standard,which provides uniform semantics for synthesis,physical implementation and verification,as well as the specific commands and methods of using UPF to describe power intention in intra prediction mode selection module,are studied.Finally,based on the physical synthesis of netlists,UPFs,and design constraints,the entire physical design flow from the netlist to the GDSII format layout file is completed using Synopsys' IC Compiler.It mainly includes important steps such as chip floorplan,power network planning,clock tree synthesis,routing,static timing analysis,and physical verification.The problems faced by each step of physical design are analyzed and discussed,and the optimization method is given.By integrating multiple low power technologies and multiple iterations of physical implementation,the design meets the expected performance indicators.The chip operates at a frequency of 200 MHz and has an area of 34884474um2 and a power consumption of 195.67 m W.Both static and dynamic voltage drops are less than 5%.