Analysis And Optimization Of The Reliability And Leakage Power Of N-type Domino Gates Circuit

The development of integrated circuit manufacturing process has further reduced the size of the device into the nano-level,which has brought some problems affecting the reliability and stability of the circuit,such as Negative Bias Temperature Instability(NBTI).The NBTI effect mainly affects the performance of the PMOS transistor,causing the threshold voltage to drift,thereby causing the circuit delay to increase and the performance to decrease.The most serious result is the failure of the circuit function.Studying how to mitigate the influence of NBTI effect on the circuit has become a very important direction in the design of integrated circuits.At the same time,the reduction in device size has also made the power consumption problem of integrated circuits more and more serious,among which the leakage power consumption problem of the circuit is the most serious problem.Leakage power can reduce the use of integrated circuits and shorten the life of integrated circuits.While alleviating the influence of NBTI effect on the circuit,how to reduce the leakage power of the integrated circuit has become an important content of integrated circuit reliability design.In this dissertation,for N-type domino circuits,the effect of NBTI effect on the performance of the circuit is experimentally analyzed.In order to take into account the noise-tolerance capability of N-type domino circuits,a method of using dual threshold voltages is proposed.A low threshold is configured on the PMOS transistor of the inverter,and normal thresholds are configured on other transistors.The simulation results show that the N-type domino OR gate logic circuit with double threshold voltage proposed in this paper has a timing margin of 0.41% after a 10-year aging period,which effectively ensures the reliability of the integrated circuit.The power consumption problem has always been an important issue affecting domino circuits,which is analyzed in this dissertation,and a structure of domino logic with clock and input dependent transistors is proposed in combination with the structural features of N-type domino circuits.A PMOS transistor with independent input is added between the pre-charged PMOS transistor and the dynamic node in the structure,which acts as a additional pre-charged transistor,and an NMOS transistor with independent input is inserted between the pull-down network and the dynamic node,which is used to control the connection between the pull-down network and the dynamic node,achieving the purpose of reducing power consumption.Finally,the result with HSPICE simulation shows that the proposed controllable domino circuit structure can effectively reduce the circuit power consumption,and the effect of reducing power consumption is getting significant with the increase in input voltage.