The Design Technology Of Power-gating Single-rail MOS Current Mode

With wide uses of integrated circuit chip in the electronic products, the problem of power consumption chip has been greatly concerned. Raising the working speed, reducing the power consumption of the chip has been become the important goal of many researchers. There are many existing power consumption reducing technology, for example, double threshold technique, channel length bias technology, input vector control and power-gating technology. Power-gating technology can effectively reduce power consumption in sleep mode, thereby reducing the total power consumption. Therefore, in order to further achieve the high speed and low power consumption, power-gating technology is applied to SRMCML, the realization of high speed circuit and reducing power consumption in sleep mode at the same time has become a very important target.This dissertation studies the design technology of low power and power consumption composition of the traditional CMOS circuit. The power-gating technology will be good to apply to SRMCML, and the circuit modeling, power-gating technology and the design of near-threshold circuit are studied to decrease power consumption of it. This paper can be divided into the following parts:1. Introduce the research background of low power design technology, and analyze the importance of research on design technology of power-gating SRMCML circuit.2. Introduce the working principle of the MOS current mode logic(MCML) circuit and circuit structure of dual current mode circuit. The performance characteristic of SRMCML circuit is analyzed for a new structure.3. Introduce the working principle and the design parameters of the traditional static CMOS power-gating technology. According to the characteristics of power-gating technology, it will be used for SRMCML circuit. Building the modeling to analyze the power consumption of powergating SRMCML circuit which in active mode and sleep mode, and the influence with the sleep transistor size varies. Design the new power-gating SRMCML sequential circuit, and optimize the power consumption. Compare the power-gating SRMCML circuit with the traditional CMOS circuit and non power-gating MCML circuit. Results show that the power-gating SRMCML circuit has advantage in reducing the leakage power consumption.4. Combine with the working characteristics of power-gating SRMCML circuit, using near threshold technology to optimize its performance. In the near threshold conditions, analyze the minimum working voltage of the power-gating SRMCML circuit when it can work normally. Compare the performance parameters of the power-gating SRMCML, MCML and the traditional CMOS circuit in different working voltage time. Experiments show that applying near threshold technology to the power-gating SRMCML circuit can effectively reduce the power consumption and the delay.