Research And Design Of Low Power Consumption Based On SoC Chip

As the process nodes of integrated circuits become smaller and smaller,the on-chip integration degree and scale are greatly improved,and the gate level units integrated on a chip can reach hundreds of millions,coupled with the significant increase in the clock frequency required by the chip operation,the resulting problems such as increased power density and excessive total power consumption are becoming more and more serious.In addition,the decrease of power supply voltage and transistor threshold voltage makes the chip leakage current increase significantly.The result of these objective conditions is that the power consumption has reached the acceptable limit of the chip.High power consumption will lead to excessive temperature during the operation of the chip,which will degrade the performance and reduce the reliability of the chip.In order to reduce the temperature of the chip,it is necessary to increase the cost to use ceramic packaging,and even need complex and expensive radiator and cooling system.High power consumption also shortens the battery life of portable devices such as mobile phones and tablets,and increases the cost of powering large electronic devices such as large computers and servers.Nowadays,power consumption has become an important factor in integrated circuit design as well as performance and area,and it is an important indicator to measure the commercial value of chips.This thesis first introduces the research background and significance of low power technology,then analyzes the power source of chips in detail,and studies the current mainstream low power design methods,including clock gating technology and multiple threshold voltage technology with relatively simple implementation,as well as the low power design method based on UPF to realize multiple voltage and power gating technology.Finally,based on a SoC project of the internship company,the low power design was carried out,and then the design results were checked to see whether they met expectations.In the design of clock gating and multiple threshold voltage,the original design architecture and traditional design flow can be used to realize these two technologies.However,when designing multiple voltage and power gating,it is necessary to plan the power domain and use special low power units.Therefore,this thesis first introduces the unified power format UPF standard and the process of using UPF for low power design,and then plans a new low power design architecture based on the original architecture of this SoC project and writes UPF files.Then DC synthesis based on UPF file is carried out and the resu lts are checked.Finally,formal verification is performed on the netlist+UPF’ after synthesis and RTL code+ original UPF before synthesis.The report of this design shows that the relevant results are in line with expectations,the use of low power technology can significantly reduce the power consumption of the circuit,and formal verification results show that the logic function of the circuit before and after the synthesis is consistent.