ASIC Clock Verification Based On System Verilog

With the rapid development of integrated circuit technology,the scale and complexity of chips are increasing day by day,and the verification workload is increasing rapidly.In the development process of System On Chip,verification takes up about 70% of the time of the whole project.Even with such a huge effort,the incompleteness of verification is still the main reason for the failure of the chip,and functional verification has become the bottleneck of the chip design and development cycle.The clock which is the fundamental premise for the realization of chip system function runs through the whole circuit.Therefore,it is particularly important to verify the clock module comprehensively and effectively.The concepts of simulation verification and formal verification methods are described,their principles are analyzed and their advantages and disadvantages are studied in depth.A method combining simulation verification and assertion verification is proposed to verify the clock module.According to the different function points of ASIC clock module,directional test,constrained randomization test and coverage driven verification method are used to check it.Through the research on the characteristics of the clock module,the corresponding improvement is made on the basis of the typical verification platform,which simplifies the verification platform and effectively reduces the difficulty of clock module IP-level verification.The work mode of the clock module is analyzed,and the functional points of the clock module under the normal working mode of the system are checked with the method of scene traversal.The performance of PLL check: including checking the output clock frequency and internal parameters in two working modes,and checking the performance of mode switching process;Register performance check: using the method of isolated input excitation vector to check the read and write performance of register;The connection of interface signal check: checking connection of register and corresponding signal in interface by the method of using a single bit to change input bit by bit,which can effectively check out the situation of serial connection and misconnection;The PHY clock source check: checking the source of all the clocks in the PHY by means of traversal.Finally,the completeness of verification is improved by analyzing the code coverage results.During the simulation test,short reset method is used to shorten the time of power on the system and accelerate the simulation process of the test case.This thesis introduces the causes of system power consumption,analyzes two working modes based on bus frequency reduction,deeply studies their working principles,and puts forward corresponding verification strategies.In this thesis,the generation of clock burr is analyzed,the characteristics of clock burr and short pulse are studied,and the verification method of assertion is used to check it.This thesis focuses on the various situations encountered in the process of code simulation,and makes an in-depth analysis of each situation,so as to improve the code.Finally,the clock signal to be checked is instantiated.The coverage driven method is used to verify the clock module to ensure the completeness of the verification.It only takes one hour or even dozens of minutes to simulate with the method of short reset,while under normal circumstances,the simulation time of the test case needs at least two hours,which significantly improves the work efficiency of verification.The code written for checking assertion is used in the actual project of the company,and as many as more than 100 clock signals are checked.It has been proved by the project that this code which can effectively make up for the omission of monitor in the verification process.is real and effective.