Design Of Low-cost Low-power Successive Approximation Analogue To Digital Convertor In PCM Codec

Successive approximation analogue to digital convertor (SAR ADC) is one of the most used ADC in the moderate precision moderate speed application, such as wireless sensor network, medical electronic, portable instrumentation, consumer electronics. In the present integrated circuit technology, the chip area, power consumption and cost of SAR ADC can be dropped to a very low level, while the precision and operating speed have been significantly improved. Thus with the further development of the integrated circuit technology, the application scope of SAR ADC will further expand. Low cost and low power consumption is the goal of this paper.Pulse-code modulation (PCM) codec chips are in 1980s and mature, but it is only limited to the research level abroad. Now most of the PCM codec markets are occupied by several well-known international design companies. PCM voice codec was one of the eighth five-year plan projects. Research was directed by several research institutions, among which Fudan University is the earliest, and their research has achieved some success, but unfortunately almost no such products enter the market. Due to various reasons, the research of PCM voice codec slowing in recent years. Although there are hundreds of analogue IC design companies at home, only Shanghai Beiling's PCM voice codec chips appear on the market at present.This thesis mainly studies a new framework implementation of SAR ADC used in PCM codec. Combining the working principle and encoding rules of PCM codec, a detailed analysis on the working principle and non-ideal error sources and its influence of the ADC is maked. Meanwhile, the implementation of PCM encoding circuit is given. For SAR ADC, the capablity of DAC and comparator influence its performance greatly, so this paper mainly focuses on the DAC and comparator design.The research work of this paper mainly includes the following parts. (1) A DAC of maximum precision for 11 bits, minimum accuracy for five bits is designed. This DAC high seven bits using capacitance array, low 4 bits using resistance array. For smaller sampling signal, the accuracy can reach 11 bits, then no compression on the signal amplitude, but for large sampling signal, the A law 13 broken line characteristic of PCM is followed. The greater the signal amplitude is, the more serious the compression is.The effective utilization of the speech signal and the characteristics of PCM, makes the switch noise greatly reduced, so does the power consumption, error rate and chip area. (2) Cascading with two-stage comparators plus three-level inverter structure is adopted for the comparator, which effectively improves its speed and resolution. The use of three-level inverter guarantees the output quickly reach logic level values the digital circuit needs. The comparator can distinguish signals with amplitude 0.4mV and frequence 500KHz, and the delay is 72ns, satisfying the PCM application. (3) The layout of comparator, capacitor array and resistor array have been designed. In order to increase the matching and reduce distortion, dummy capacitors and resistors have been used in the layout.The design uses CSMC 2P1M P well CMOS mixed signal process with power supply 10V. Only nine masks and twelve photolithographies needed when fabricated. Design and simulation are completed under cadence Spectre simmulator. Simulation results show that the power consumption is 8mW at 8KHz sampling rate, dynamic range 43dB, signal to noise rate (SNR) accord with CCITT specifications established for PCM codec system.