Research And Design Of Radiation-hardened SRAM

With the development of semiconductor technologies for integrated circuits and the reduced feature sizes for semiconductor, the memory is more and more susceptive to the single event upset(SEU) effect caused by radiation particles under radiation environment. Research on SEU of semiconductor devices and methods to improve the capability to resist it is of great significance to enhance the reliability of memory.The basic theory of SEU effect has been introduced firstly, followed by the operating principle of the conventional 6T SRAM cell. This paper proposes a new 12 T SRAM cell which aims at avoiding the situation that the data is vulnerable to external noise during read operation. The data storage nodes are isolated from the bit lines, thus improving the stability of 12 T SRAM cell greatly. The SEU immunity is enhanced by adding redundant nodes. The redundant nodes maintain a source of uncorrupted data after an SEU and can provide specific “state restoring” feedback to recover the corrupted data. HSPICE based simulation verify the read and write operation, read speed, stability and power dissipation of the SRAM cell. Linear energy transfer can be used to measure the ability of SEU immunity. The hardness is validated using mixed-mode simulation with Sentaurus TCAD. Finally, the commonly used structures of SRAM peripheral circuits, such as sense amplifier, address decoder and address transition detector are analyzed briefly. A 4Kb asynchronous SRAM is designed and gives the simulation results.