The Optimization Of Static Leakage Current Of Sram Based On 40 Nanomer Low-power Process

With the scaling of transistor size,the static leakage current of SRAM(Static Random Access Memory)becomes significant concern.The static leakage current of SRAM is the highest contributor to the power consumption of the SOC(System on Chip)chip.Thus finding ways to reduce SRAM static leakage current is the key to achieve the low-power consumption.Based on the 40 nm low-power process,this paper designed series of experiments to realize the significantly reduction of SRAM static leakage current by optimizing the halo structure of NMOS in SRAM cell.The conventional halo structure of NMOS is formed by two-step ion implantation process,the first step uses boron atoms as the ion implantation source,and the second step uses indium atoms as the ion implantation source.The indium implantation in the second step will bring two disadvantages: 1)the enhancement of electric field in the PN junction due to the low diffusion of indium atoms results in an increase in BTBT(Band To Band)tunneling current.2)The introduction of interstitial silicon atom during indium implantation will degrade device performance.As to the disadvantages of conventional halo structure,this paper proposed a new way,skipping indium implantation and forming the halo structure just only by boron implantation,to optimize halo structure.With such kind of way,the static leakage current of SRAM can get improved due to the significant decrease of PN junction reverse–bias current of NPD(NMOS Pull Down)and NPG(NMOS Pass Gate)transistor.The experiments results indicate that skipping indium implantation plus higher boron implantation energy can reduce the static leakage current of SRAM.Finally,the static leakage current of one SRAM cell decreased to 28.4pA from 41.1pA with comparable cell performance,realizing the leakage current decline of 30.9%.