The Method's Research And Application Of BIST-based Internal Delay Fault Testing In FPGAs

Today in the rapid development of integrated circuits, the Field Programmable Gate Array (FPGA) has become an indispensable digital integrated circuit chip because of its variability, reusability and efficiency of IC design. The FPGA greatly reducing the time of the chip from design to prototyping compared to the traditional ASIC design. Meanwhile the SRAM-based FPGA can be used in many times in the chip design until successfully design. This is greatly reduced the risks of failure of silicon and time from design to prototyping. Therefore, FPGA devices have become one of the most popular devices.With the extensive application of FPGA, FPGA testing technology has been extensively attention and research. FPGA-based programmable features, application-independent (manufacturing) testing of FPGAs requires a number of test configurations and test vectors in order to guarantee the functionality of the chip for all possible configurations. the structure of FPGA becomes more complex. a large number of faults is difficult to use traditional methods for testing, requiring FPGA designers start to pay attention to the problem of design for testability(DFT).DFT solution for the large-scale integrated circuits to test problem has opened up a new and effective way, and one of the important technologies of DFT is Built In Self Test.According to the above problems, firstly make the Xilinx FPGA family to the main object of study. This dissertation introduces the structure characteristics, fault models and testing techniques of FPGA devices, and focuses on the principle structure characteristics and theories of BIST and BIST test design and application., this paper introduces FPGA devices BIST delay fault testing techniques and methods, given FPGA delay fault testing configurations, Then BIST testing structure circuitry is presented, and through ISE software simulation shows the validity of the method. Finally the paper introduces some of the issues on the characteristics of dynamic reconfigurable FPGA to be resolved.The result of this research provides a great guarantee to the design of FPGA devices, and gives a big contribution to the FPGA testing research.