Research On The Hierarchical Test Methods For The SoCs

With the development of VDSM (Very Deep Sub-Micron) manufacture technology and the reuse of IP (Intellectual Property) cores, The SoC (System-on-Chip) design method becomes more and more popular. With the advantages of more powerful functions, smaller cube, lower powers consume and the shorter development period, SoC is providing greater market demand. But the test and verify of SoC become more and more difficult because of its extreme complexity, very high frequency and the use of IP cores. The test of SoC includes many aspects: Design For Test(DFT), Fault Model, Auto Test Pattern Generator(ATPG), Test Wrapper Design and Optimization,Test Access Mechanism (TAM) design and Optimization,Test Schedule,Circuits Design for Test(e.g BIST-Built-In-Self-Test, LFSR-Linear-Feedback-Shift-Register), etc.In this paper, we will pay our focus on the following five aspacts: how to simplize the computation of the SoC interconnect model; how to develop more effective fault model of interconnect and its implementation in hardware; how to design test wrapper of IP core which can be used in hierarchical SoC; how to design and optimize the test wrapper which can support multi-frequency fashion; how to design and optimize TAM in hierarchical and multi-frequency SoC and how to develop an integration design flow including the above arithmetics so that the test time and the test hardware are both minimal. The following parts will give a brief introduction about those researches.With the reductive distance between wires and the increaseing frequency of SoC in deep submicron technologies, the coupled noise of interconnect becomes more and more serious. However, the presented computation methods are either too complicated or too inaccurate. Based on the in-deepth researches on the presented methods, this paper presents a new effective method to compute the coupled noise; the results between this method and HSpice simulation are also presented in the paper for comparison.We presents two simple and efficient fault models to stimulate and detect crosstalk faults on interconnects between IP cores based on the in-depth researches of crosstalk fault and the presented fault models.The theoretic analysis is also given out in the paper to show the two models'efficiency. Two implementation methods based on software and BIST are also presented with the software flow; the area overload of test pattern generator and test respond analyzer as well as test controller are also presented.Based on the in-depth researches of the related documents, this paper presents a new test wrapper design for hierarchical SoC which can meet with the IEEE 1149.1 and the IEEE P1500 standards. The detailed analysis for hardware overload and test controller are also presented in this paper.This paper presents a new test wrapper design and its optimization arithmetic for multi-frequency SoC based on the presented researches. Experimental results are presented for ITC'02 SoC.The TAM design and optimization scheme are presented for hierarchical and multi-frequency SoC based on the above multi-frequency wrapper design arithmetic, the integration design flow is also presented in the paper.