The Research On Delay-Fault Testing Technology For FPGA

Field Programmable Gate Array (FPGA) is a field programmable ASIC, which integrates a Generic gate Array structure and the characteristics of field programmable together.Now, FPGA devices has become the most popular devices. With the extensive application of FPGA,FPGA testing technology has been extensively attention and research.FPGA-based programmable features, application- independent(manufacturing) testing of FPGAs requires a number of test configurations and test vectors in order to guarantee the functionality of the chip for all possible configurations.Therefore,the FPGA device fault testing and fault diagnosis method for a more comprehensive study is of greatsignificance.With the fast expand of FPGA devices,the structure of FPGA becomes more complex.a large number of faults is difficult to use traditional methods for testing, requiring FPGA designers start to pay attention to the problem of design for testability(DFT).DFT solution for the large-scale integrated circuits to test problem has opened up a new and effective way, and one of the important technologies of DFT is Built In Self Test(BIST).According to the above problems,firstly,IEEE Standards IEEE-Std-1149.1 to 1149.6,IEEE-Std-1450,IEEE-Std-P1500,IEEE-ISTO-Nexus 5001 are presented. Analysis of the characteristic of each standard is summarized in this dissertation,then design and simulate the structure of boundary-scan test.this will be of guiding significance on the VLSI test theory and test technology;Secondly,this dissertation researched the technology of testing FPGAs.Based on a detailed analysis of the architechture of Xilinx FPGAs,this dissertation introduces the structure characteristics, fault models,testing configurations and testing techniques of FPGA devices,and the principle structure characteristics and theories of BIST.This paper focuses on BIST test compression algorithm,design and application.Then BIST testing structure circuitry is presented,and through ModelSim software simulation shows the validity of the method. Finally, this paper introduces FPGA devices BIST delay fault testing techniques and methods, given FPGA delay fault testing configurations, and comparison analysis of the current popular FPGA BIST methods and some of the issues on the characteristics of dynamic reconfigurable FPGA to be resolved.The result of this research provides a great guarantee to the design of FPGA devices, and gives a big contribution to the FPGA testing research.