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The Research On Delay Test Vector Generation Method

Posted on:2015-12-24Degree:MasterType:Thesis
Country:ChinaCandidate:S W DingFull Text:PDF
GTID:2428330488499558Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
In the process of IC manufacturing,the IC(integrated circuit)test is the indispensable link.It not only ensures the correct logic of IC chips,but also ensures to make the right responses during the prescribed period of time.With the constant improvement of the work frequency in IC system,a small manufacturing error can affect the reliability of the chip.Therefore,the delay test to ensure the accuracy of IC timing characteristics also becomes an important issue in the test field.In this paper,the delay fault model can be considered as small delay fault model and transition dealy fault model.There are two kinds of delay fault model in this paper that is small delay fault model and transition delay fault model.It proposes a new method to reduce the test generation time and to improve the fault coverage on the small delay fault.Meanwhile,it develops a test generation method to gain high fault coverage.Firstly,based on the relationship among the nodes in circuit,it proposes a method to guide the process of test generation by using the statistical information.The proposed test generation method utilizes the self-growth on path selection to reduce the search space of path.At the same time,it reasonably groups the path through faster than at-speed in order to improve the testability of path.The proposed statistics method can judge unknown information in advance in the process of test generation,thereby effectively avoid the occurrence of small probability events.Therefore the test generation time can be reduced and fault coverage can be improved.The results of testing on ISCAS'89 benchmark circuits show that the proposed method can increase the small delay fault coverage about 1.3%and save time about 9%.Secondly,reasonable using the test generation method on stuck fault,it designs a test generation method on transition delay fault that has high efficiency.The approach transforms the single frame circuit structure to the double frame circuit structure.It make the test vectors satisfy the requirements of skew load delay test vectors and transforms the transition delay fault test to the stuck fault test.Meanwhile,it applies the statistical information among nodes in circuit in the process of test generation,further improving the transition fault coverage.The results of experiment on ISCAS'89 benchmark circuits show that the proposed method can prove the transition fault coverage about 1.02%on average.
Keywords/Search Tags:IC, Small delay fault, Test generation, Fault coverage, Transition delay fault
PDF Full Text Request
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