New pseudo random testing techniques for scan-based built-in self-test

Rapidly growing of VLSI designs increases the testing cost dramatically. Testing circuits using external automatic test equipments becomes expensive and less accurate because of the limitations in speed, bandwidth and vector size capacity. Built-In Self-Test (BIST) eliminates these problem by adding special test circuitry on chip. The test equipment only requires to provide clock and a few control signals instead of the complicated operations of porting the test vectors. BIST based on pseudo random testing is particularly attractive as it costs relatively low hardware overhead.; BIST for regular structures such as memories has reached a good level of maturity. For random logic, there is still plenty of room for innovation. Pseudo random testing for scan-based BIST is a low-cost BIST method, however, its test quality is usually unacceptable. In this dissertation, we propose several techniques to address this problem.; Test point insertion is a technique which modifies the circuit so that it becomes more random testable during the test mode. We present a test point selection algorithm based on a novel cost function. The cost function faithfully reflects the testability improvement and can be computed efficiently with the proposed algorithm. The algorithm is also capable of generating test points for partial scan circuits.; We further propose two non-intrusive design for testability solutions for scan-based BIST. An almost full-scan design methodology is introduced specifically to maximize the pseudo random testability of scan-based BIST. Better test results are achieved by this method as compared to the original full-scan-based pseudo random BIST. We also present a general test application scheme that uses the test application time budget more effectively for high test quality. Under this scheme, an effect similar to multiple-weight-set weighted random testing is produced without special hardware.; Testing timing related defects becomes increasingly important as the circuit speed moving higher. Path delay fault model is considered as a more realistic fault model as it captures the small and distributed timing defects. To improve the path delay fault testability under pseudo random testing, we first introduce a path delay fault testability metric. We demonstrate that the metric is reliable and the computation of the metric is efficient. We then use this testability metric to derive a path delay fault test application scheme for pseudo random scan-based BIST. The results demonstrate that using this test application scheme, a better path delay fault coverage is obtained.