Research Of I_DDT ATPG Algorithm Based On Ambiguous Delay Assignments And BIST Test Pattern Generator Design

IC testing is critical for high quality ICs and high yield of IC production. Testing based on stuck-at fault model is insufficient for high performance ICs, especially for CMOS circuits. Quiescent power supply current (IDDQ) testing has become an accepted test method by the IC industry since the idea was published in early 1980's. However, some defects, such as some stuck-open defects in CMOS ICs still cannot be detected by IDDQ testing or by logic testing. This limitation motivates the introduction of transient power supply current (IDDT) testing.In fact, gate delays may not be the same even for a same manufacture process and a same kind of gates. So, the test patterns generated according to fixed gate delay assignments may not activate faults, or weaken the difference between the average IDDT value of a fault-free circuit and a faulty circuit in real test applications. This thesis proposes a new test generation method to make the test patterns activate faults and hold the difference unvaried even though the gate delays are assigned randomly within a certain bound. The 95% of the test patterns generated by the new approach are proved to be valid by our experiment, even though gate delays are assigned randomly from 50% to 150% of their nominal values.Furthermore, we improved the FAN algorithm ulteriorly on the precondition of considering the influence of the gate delay assignments to the IDDT testing sufficiently. By tracking the lines which are assigned D or /D, we can evaluate the effect of hazards to the IDDT testing and weaken the negative effect of hazards. The validity of testing vectors has been improved and testing time was decreased by this way.This thesis also proposes an efficient BIST test pattern generator design based on IDDT testing by following my prevenient work. In my design, the regular, modular and cascadable structure of cellular automata (CA), instead of linear feedback shift register (LFSR), has been utilized as a pseudo-random pattern generator. Cellular automata and two shift registers are assembled elaborately together to generate two-pattern vector. The BIST combining with IDDT testing method is proved to be valid and fast for testing stuck-open fault in CUT by the experiment.