BIST-Based Delay-Fault Testing Of FPGA Device

With the speedy development of Very Large Scale Integrated Circuits (VLSI), 90-nanometer technology has been applied to current Integrated Circuits (IC) manufacturing. Numerous chips that contain more than 10 million gates are being produced. Smaller and smaller the chips packages becomes, denselier and denselier the chip pins place, and more and more components the Printed Circuits Boards (PCBs) assemble on. As a result, interconnect testing of chips is in urgent need to resolve. On the other hand, there are a large amount of nodes, which are inaccessible from outsides, within chips or functional blocks. Testing such inaccessible nodes or blocks is a challengeable task. With the faster progress of VLSI technology, testing circuit boards by external devices has become more difficult than before, DFT proposed in recent years is an efficient way to overcome IC test difficulty. In order to make test and diagnosis of digital system go along rapidly and efficiently. Self test method often carries out under software. But a pure software self test method that can meet request at system level has some disadvantages. This test method may have bad diagnostic differentiation. Besides a nicer software test may have long development time and large workloads. A method that carries out self-test under hardware is paid attention. But successful application of BIST technique in FPGA reported in literature is much less than their engineering actual demands. Author's researching in this thesis is rightly based on above facts. BIST theory, solution and application in FPGA are studied in this thesis. Work focuses on test algorithm, design, usage.Design principle and methodology of DFT in BIST are discussed, Based on above principle and methodology, test stimuli generation and test response analysis of BIST are studied. This paper presented an altering BIST Structure. Test vectors generation algorithm based on generation algorithm (GA) and linear feedback shift register (LFSR) is presented. It can not only improve test rate but also get low power. Discussion is placed focus on built in self renovate (BISR) circuits design. Embryology model is presented. At last, an example is proposed to validate this...