Deterministic BIST And Delay Fault Testing For Digital System

The testing of integrated circuits is an emerging issue in Microelectronics. DFT (design for testability) method tries to resolve the test problem in the early process of IC design. BIST (built-in self-test) is an important DFT technique. In this thesis, we research on scan-based BIST techniques of digital systems. Path delay fault testing can detect lots of defects that can not be detected by the test patterns targeting stuck-at faults. We also research on the fault simulation of path delay fault.A scan-based BIST scheme based on the scan-forest architecture and weighted scan-enable signals is proposed to acquire complete fault coverage of single stuck-at faults. The proposed BIST scheme relies on a pseudo-random testing phase and a deterministic phase. A new testability measure is presented to guide test generation such that test patterns with fewer care bits are obtained. For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.A fast and exact fault simulator is proposed for path delay faults. The proposed fault simulator constructs SPC (selected path circuit) based on non-robustly testable or robustly testable path set. Fault simulation is reduced to logic simulation on the original circuit. By effectively pruning the SPC, we propose an effective fault dropping technique with a backward selective tracing scheme. Additionally, the pruning process raises the speed of fault simulation, while assures the exactness of fault simulation.