Design And Implementation Of USB Controller And General Purpose IO Interface Controller IP Core For SoC

With the development of Integrated Circuit technology, the chip's density rises very quickly. A system, which consists of microprocessor, coprocessor and some other peripheral chips, could be integrated into one chip. The technology of one chip containing a system is called System-on-a-Chip (SoC). Nowadays, SoC technology has drawn great attention of the computer circles and the electronic engineering circles.Because SoC chips' density and frequency are getting higher and higher, and their time to get into the market is getting shorter and shorter, the designers incline to depend more and more on IP core in the designing of SoC chips. IP cores are of great importance in the SoC field, and are regarded as the groundsill of buildings. The methodology of IP core includes not only all classical techniques of IC such as test, verification, simulation and low power, but also many new research fields.The controllers of Universal Serial Bus (USB) and General Purpose 10 Interface (GPIO) are the two very important peripheral controllers in SoC field. This paper concentrates on the soft core, firm core and hard core of USB controller and GPIO controller. GPIO IP core has been integrated into Estarl embedded microprocessor which was taped out successfully, and works well during the course of test. USB IP core will be integrated into a SoC chip and taped out next year.The algorithm of Parallel Cyclic Redundancy Check (PCRC) is introduced to solve the problem of Cyclic Redundancy Check in USB IP core. The implementation of PCRC5 and PCRC 16 modules not only reduces the complexity but also acquires considerable speedup of the hardware.The techniques of configurable number of endpoint and configurable capacity of memory are realized in the designing of USB IP cor-e. They are simply configured through text macro before synthesis. Moreover, the performance of USB IP with diverse endpoints is analyzed and evaluated based on FPGA implementation. Two configurable characteristics of USB IP markedly strengthen the scalability and adaptability for diverse SoC chips.The method of Bus Adapter and IP Core with Configurable Bus Interface is proposed to improve the reusability of IP core. This method is applied to design the USB IP core with configurable bus interface, and to design and verify three bus adapters, that's to say, WISHBONE, AMBA APB and typical uProcessor interface. The method enhances the reusability of USB IP core, and makes it easily adapted to many SoC with diverse OCBs. What's more, the performance of USB IP with diverse bus adapters is analyzed and evaluated based on FPGA implementation.The technique of Direct Memory Access (DMA) is presented to achieve high-speed datatransfer in GPIO controller. The DMA control logic that communicates with DMA controller is integrated into GPIO IP. The technique of "Serial-In-Parallel-Out" is adopted in the GPIO IP to improve data throughput rate. The test result on actual Estarl chip indicates that the data transfer rate of GPIO IP can arrive at 30MBps.Static Timing Analysis is the key technique that ensures success of SoC chip designing. The method of fixing violations of hold time and removal time is proposed in this paper. This method has fixed timing violations in Estarl chip and guaranteed the success of it. Besides, the method is applied to the designing process of USB IP and GPIO IP, and obtains good results.The achievements of this paper have important practical and realistic significance to IP core design and implementation in SoC field.