Research And Design Of The GPIB Interface IP Core Based On FPGA

With the developing of micro-electronics technique, the ISP (In System Programmability) has penetrated into various areas and won wider and wider popularity. The solutions proposed by Altera, which is constructed upon SOPC (System On a Programmable Chip), made FPGA (Field Programmable Gate Array) count more and more in the design of imbedded system. With the help of SOPC, the necessary components such as CUP, memorizer, I/O interface, LVDS technique, CDR and PPL can be integrated into certain programmable chip which is called programmable system..The GPIB (General Purpose Interface Bus) is a kind of interface exclusive to devices, which following the lastest standard is IEEE488.1-2003 and IEC/IEEE 60488-2(2004).GPIB takes the role of bridge towards the construction of auto-detect system. Now GPIB is applied widely in testing because of the following advantages in constructing auto-detect system: constructing smart, convenient, small scaled, high device efficiency, high reliability.This thesis is composed mainly by two parts: the first part concerns the function implementation of GPIB interface by means of GPIB interface's exclusive chips. Under the control of Winbond's W77E58 singlechip, TNT4882 can guarantee the function of GPIB interface. Serial port is connected by MAX232 and RS232. The interface of P1.0 and P1.1 can be connected with RS232's CTS and RTS through MAX232. Based upon the above design, the single chip is able to control the data stream of RS232, adjust the transmission speed between GPIB and RS232, and also grants the conversion between RS232 and GPIB protocol.The next part mainly deals with the IP core design of GPIB interface. Now that profound knowledge is available via the reference of the first part, the IP core design of GPIB port can also be available. Based on the theory of modularization, the IP core of GPIB is divided into three modules: module for port function of GPIB, module for inner register and module for data transmission. The port function of GPIB is realized by means of state machine. The function is defined by a set of repulsive and correlated state graphs initially, and then with the help of the illustrated functions and the gemel among the states, the design of state machine for GPIB chip is available. In order to take charge on port function of GPIB and data transmission, the designed 8-bits control registers and status registers, which controls the port function of GPIB and inquire about the port status and interrupt status of GPIB separately, mount up to 25. According to the criterion of Avalon bus, by which the IP core of GPIB interface can be connected with it, this thesis designed the port signal for the control of IP core, and two more FIFOs are designed to adjust the transmission speed between Avion bus and GPIB.The designed RS232-GPIB protocol transformer is applied in the high-power semi-conductor device characteristic instrument successfully, and IP core design of GPIB interface core has also be verified efficient through ModelSim and Quartus.