Research Of 8051-compatible Core Based Processor IP With AHB Bus Interface

Amid at SoC systems with performance need ranging 10-100 MIPS, optimization research was made upon the 8-bit 8051 compatible microcontroller core.In order to take advantages of existing 32-bit commercial SoC bus compatible IP resources as well as the supporting hardware/software development tools, AMBA 2.0 bus standard was specifically selected. AHB bus interface was added to one 8051-compatible core, which enables the capability to be used in AMBA-based SoC integration in the form of standard AHB master IP. A bridge module was designed to convert protocols between 8051 inter bus and AHB bus. The finished processor IP can seamlessly substitute the original 32-bit processor IP to build low-cost SoC solutions as well as accelerate system development.At the same time, 0.18um on-chip embedded FLASH was integrated as program ROM, which takes the advantage of newly developed memory process and increases system programmability. Lately, ICACHE was added as a solution to increase performance after the analysis of performance bottlenecks. Parameterized ICACHE model was developed to help the analysis, which collects information on the relations between system characters and ICACHE parameters. Based on the result of analysis as well as design constraints, design parameters were determined and a 128-byte, direct-association ICACHE was further implemented. The optimized IP can thus run up to speed of 176 MHz, nearly 3.7 times the original design without ICACHE, which can run at 47.4 MHz and with peak performance of 11.85 MIPS. Significant performance improvement is made in the cost of limited area overhead.This processor was developed under minimum modifications to the inner logic of the original 8051-compatible core. Further optimization can be expected to increase its value. Further more, future researches can also take the advantage of this process IP.