The High-Speed Interconnection Structure Design And Implementation For Multi-Core Array

With the improvement of the integrated circuit density, the complexity of the components in the system has increased sharply. In order to cope with the increasing transistor density, higher clock frequency, lower power consumption, and the pressure of the market, semiconductor industry paid more attention to multi processors in one chip or multi processors in multi chips rather than single processor. At present most of the multiprocessors connected by bus. However, when the number of processing elements increase to a certain size, system designers may face unprecedented challenges in the design of the interconnets. Traditional bus-based communication schemes, which have the existence of inevitable data conflict, lack of scalability and predictability, cannot meet the demand of the future multicore systems in the performance, power, timing closure and extensibility, etc. Therefore, designing an efficient high-speed interconnection structure is a key of multi-core processing system.In this paper a high-speed interconnect structure for multi-core array has been designed and implemented on the hardware platform. The design mainly adopts the way of on-chip network interconnection, when across different chips or boards, high speed serial interface is used for data conversion to expand the scale of the multi-core. Firstly, this paper studys the serial high-speed interconnection interface, and introduces several of the key points in serial high-speed interconnect interface, such as clock recovery, serialparallel data conversion, data coding, data synchronization, etc. Then the steps of testing the serial high-speed interface on the hardware platform by Xilinx’s IBERT Core are provided. The test results show that the BER is superior to8 E-14. At the same time the self-defined protocol and SRIO protocol test results are normal. Secondly, NoC is introduced, paper compares the design of routing protocol, exchange structure, reliability and other key components, and choses the scheme which balance the performance and implementation complexity. After that, this paper gives the corresponding hardware practice of NI, router, frame format and cache size, then a solution to connect NoC to serial high-speed channel is been proposed. To make the design complete, SRIO channel is used to collect system’s data and status to main FPGA and distribute data from main FPGA, fiber channel is used to interconnect PC and FPGA. Then the baseband processing of LTE-A wireless communication system base station side is been mapped to the multi-core platform, and completes the CoMP test. Finally, a 32 cores system with vector processors is been built for testing the exchange capacity, the result shows that the system meet the requirements of project indicators.