Usb 2.0 Otg Ip Core Research And Design Of Full-speed Host Controller

An increasing number of portable peripherals are using the USB interface to communicate with the PC, but the USB interface does not support the direct communication between two peripherals generally. However, with the release of OTG supplement, this problem is resloved. The USB OTG dual device which support OTG supplement can be either host or device. So the direct communication between two dual devices can be achieved while does not need the PC. This paper discusses about the design of USB2.0 OTG IP core based on ARM. And it is mainly about the design of the full speed host controller and the verification of the IP core.The USB2.0 OTG IP core support the protocols below: the USB2.0 specification, the OTG supplement, UTMI+ specification, Open Host Controller Interface and Enhanced Host Controller Interface. This IP core is connected between the memory controller of ARM and the PHY which designed base on UTMI+ to communicate with the other OTG device.The USB2.0 OTG IP core mainly includes OTG Controller(OTGC), Enhanced Host Controller(EHC), Open Host Controller(OHC) and Device Controller(DC). The OHC which designed base on the standard OHCI specification has bus control capability. It hebaves as a master. But the IP core which is independent on MCU acts as an interface which does not have bus control capability. And the data transfer between its buffer and MCU is achieved through the interrupt which initiated by the IP core.So it behaves as a slave. Therefore in the design of the OHC, the transaction scheduling and the data structure which describes the endpoint descriptor and transfer descriptor need be improved to achieve the full speed host controller without bus controll capability. And the data structure is changed from chain list stored in the outside memory to sequence list stored in the inside buffer.I am charging for the design of the full speed host controller and the verification of the IP core. The OHC includes OHC_GR, OHC_USC, OHC_LPB, OHC_BC, OHC_SIE and OHC_RH. OHC_GR controls the soft and hard reset. OHC_USC controls the USB status transition. OHC_LPB completes the USB host transaction scheduling. OHC_BC controls the access of the buffer by OHC_LPB and OHC_SIE. OHC_SIE is charge of the USB transfer types, including assembling and analyzing the packets. OHC_RH is used to detect the device connecting and disconnecting, reset, suspend and resume the device.The VIP of Synopsys which acts as USB OTG dual device is used as the stimulus in the side of UTMI+. And the other side is ARM(s3c2410) of whose main function is used is memory controller, DMA controller and interrupt controller. Only coding these controllers in behavior to reduce the verification complication of ARM side.The FPGA test of this IP core has two steps, the first is testing the high speed host controller(EHC), full speed host controller(OHC) and device controller(DC) independently. When the IP core can operate as both USB host and device, test the IP core with OTG controller to make sure the USB2.0 OTG IP core can achieve the OTG function. And now we have achieved the function of the full speed host controller, the files can be transferred successfully in the FPGA test.