The Three Phases High-voltage Power MOS Gate Drive Integrated Circuit

The emerging of smart power integrated circuit (SPIC) is important to increase the system抯 reliability and reduce its cost, weight and volume. It enables the design and production of even more miniaturized and smart systems for different applications in the field of automotive, industrial and telecommunication. In this paper, a three phases high-voltage power MOS gate drive integrated circuit has been researched and designed successfully. It is a typical SPIC, which could be widely used in high power motor control and switching power supply applications. The design goal of the circuit are V0FFsET(max) is 500V, Ia(m~) is 1 A, the highest frequency of operation (f(~x)) is 100KHz. The drive circuit抯 experiment has been done and the result is satisfied. Now this circuit has been transferred to Sichuan Solid-State Circuit Institute. A thin epitaxial layer (10gm) LDMOS device used N-burry layer structure was proposed in the paper during the high-voltage device design, which is helpful to improve the drive circuit抯 technology. The main work of the author includes the drive circuit design, research of high-voltage LDMOS device which breakdown voltage is 1000-1200V, the drive circuit抯 technology design and layout design, technology experiments of device and circuit.During the circuit design, author analyzed the requirement of the driver for power device, and designed its general structure. The design of the circuit抯 key parameters including pulse width in the level shifter part and delay time of the filter circuit, and the necessity to add a limiting current resistor at source the LDMOS were emphatic analyzed. Author finished the design of each sub-circuit. The circuit抯 typical applicative connection was given at last.During the high-voltage device design, the thick epitaxial layer LDMOS which is compatible with current technology was researched. This device used piecewise VLD and multiple region structure F reduce field layer. The using of the F reduce field layer effectively reduce the surface electric field of the device, shorten the length of its drift region, enlarge the choice of range of the ion implant dose of the P layer, and effectively restrain the disadvantageously affection on the breakdown voltage of the interface charge Qss. Consideringthe shortcoming of thick epitaxial layer technology, author proposed a thin epitaxial layer LDMOS used N-burry layer. Through optimizing the N-burry layer抯 length and impurity dose will increase the device抯 breakdown voltage. The two structure LDMOS was compared by simulation with MEDICI software. The result is that their breakdown voltage is almost the same and the thin epitaxial layer LDMOS抯 Ron is lower.Based on the standard 2j.im P-well CMOS technology, after referenced the epidemical BCD technology in the world and considered the specialty of the circuit, the drive circuit抯 high and low voltage compatible technology was designed. Author also formulated the design rules and finished the device抯 and circuit抯 layout design.Author has accomplished the experiments of high-voltage devices and drive circuits. The test results show that each parameter of the devices and circuits fulfihle the anticipative demand; some parameters even exceed the demand.