.400 V-thin Layer Of Soi High Voltage Device

SOI HVIC(Silicon On Insulator High Voltage Integrated Circuit) is the mainstream and trend of the Power Integrated Circuit(PIC) due to the improved isolation, high speed performance, low power dissipation, perfect irradiation hardness and facility of compatible process. SOI lateral high voltage devices are the key devices in SOI HVIC. Its low vertical breakdown voltage limits the application in high voltage and power integrated circuit. A lot of novel structures have been proposed to enhance the vertical breakdown voltage of SOI lateral high voltage devices.This thesis presents a linear variation of doping, thin film SOI high voltage device structure, with SiO2 buried layer thickness of 3μm, the top silicon layer thickness of 1.5μm, and the channel length of 3μm. The drift region is etched by LOCOS technology to 0.3μm, so the vertical ionization integral path is shortened and the carriers are difficult to be accelerated to the level required for impact ionization, thereby increase the critical breakdown electric field and vertical breakdown voltage. And the drift region is linear doped, with gradually increased doping concentration from Pwell to drain. This structure offers a good optimization of the surface electric field. Gate electrode extends onto field oxide to form a field plate, it can adjust the electric field on one hand, on the other hand, the gate electrode attracts the drift region electrons to form an accumulation layer on open state, which improves the conduction characteristics. In addition, the source metal can also be taken as a field plate, which depleted the drift region together with substrate from two directions. The source plate makes it possible to achieve a doping level doubled the normal structure, which greatly reduces the device's turn-on resistance.The influence of drift region length and doping concentration slope, the thickness of drift region, the concentration of Pwell, the source field plate and gate field plate location are simulated and optimized by MEDICI. With drift region length of 50μm and concentration slope of 3.6×1015cm-3/μm, the structure can achieve a breakdown voltage of 680V and the specific conduction resistance of 62.4m? ? cm-2, which is 35% less than the structure without field. The gate field plate also eliminates the Kink effect, thus makes the output curve more flat.On the bases of theoretical analysis and device simulation, the SOI-based low-voltage and high-voltage compatible process is developed and verified by Tsuprem4, and the layout of the device is finished. This thesis also gives the specific steps and mask definitions of key processes.