| Smart power integrated circuit (SPIC) is widely used in electronic lighting, motor driver, power management, industrial control, display driver and so on. As an important branch of SPIC, motor driver chip is always an issue worthy of researching. How to reduce the power consumption and improve the performance is the development tendency of motor driver chip. This paper focuses on two research hotspot about the motor driver chip, namely pre-driver chip and high voltage power drive chip. In view of the existing design difficulties, combining with domestic manufacturing technology, put forward the corresponding solutions. And as the core device of SPIC, its reliability is becoming more and more critical and directly determines the working life of the SPIC. Therefore, the investigation on reliability issue of high voltage power MOS has great significance.The main work and innovations of this paper include:1. Research of some difficulties encountered in design of the Brushless DC Motor Pre-Driver, including no cross conduction between high-side and low-side drivers, no cross conduction within driver output stage, reduce the consumption of the high-side driver, below ground protection in recirculation and reduce the propagation delay. And the solutions are proposed. Based on the HHGrace0.35μm5V/80V BCD process, the whole chip has been verified. Test results show that the design is proved to be right. And the key performance parameters (input propagation time, rise/fall time and turn on/off peak current) can be compared with foreign similar product.2. Research of the high voltage driver chip used in frequency conversion air conditioner, including low voltage control circuit and high voltage driver circuit, high voltage power devices and the1μm500V SOI BCD manufacturing process. In SOI LIGBT design, dual-channel SOI LIGBT with N+buried layer is proposed. It not only has large current driving capability, but also has the good ability to resist latch-up, improving the working reliability of the device and the whole chip. Finally, the manufacturing process is optimized by TCAD simulation, and all the device structures are determined. The ovearall simulation results show that the design can meet the performance requirement. 3. Research of the reliability of the SOI LIGBT. The hot-carrier-induced (HCI) degradations of SOI LIGBT are investigated in detail by DC voltage stress experiment, TCAD simulation and charge pumping test. For DC stress condition, several degradation mechanisms are proposed:(a) for fixed Vce, the effect of positive oxide-trapped charges becomes severe by increasing Vge. And as the Vge decreases, interface states dominate the degradation;(b) for fixed Vge, the degradation will be worse by increasing Vce. For AC stress condition, experiments show that the Ron degradation is enhanced by increasing the gate pulse stress frequency due to the effective AC stress time f×tr. And large duty cycle produces more severe Ron degradation because of more stress. Furthermore, the influence of the pulse rise/fall times on the Ron degradation is also studied. It has been discovered that short pulse rise/fall times imply much more serious hot-carrier degradation because of the inconsistent between the turn-off speed and the decrease of the hole current. The hole current density is largely dependent on the minority carrier lifetime. The research results are great value to improve the device reliability evaluation system. On the basis, SOI LIGBT with high reliability is designed for plasma display panel (PDP)160V row driver IC product. Test results show that its normal working lifetime is more than100,000hours, meeting the requirements of the National Science and Technology Major Project (2009ZX01033-001-003). |
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