Research On The Characteristics Of LDMOS Under ESD Stress In High Voltage Integrated Circuit

ElectroStatic Discharge (ESD) is still a serious threat to the Integrated Circuit (IC).Since the ICs are widely used in electric equipments, the financial loss caused by ESDis very large. So, ESD robustness of IC has been a problem which must be solved in ICdesign to reduce the related loss. Recently, the ESD robustness of Power IC is animportant research topic with its widely application and rocketing development. Theformer research on the ESD robustness mainly focused on the low voltage ICs anddevices, while for the high voltage ICs, the relative study is still immature. Specifically,LDMOS (Lateral Diffused MOS) is popular in high voltage ICs, because it is prettywell compatible with the CMOS process. So studying the characteristics of the LDMOSunder ESD stress is an important issue to reduce the cost of IC development andimprove the robustness of ICs.In this dissertation, based on0.35μm40V/20V/5V BCD (Bipolar/CMOS/DMOS)process, the TCAD simulation, TLP (transmission Line Pulse) test, HBM (Human BodyModel) test, and failure analysis were used in order to study the characteristics ofLDMOS under ESD stress. The width direction non-uniform conducting model wasproposed. Based on it, several novel structures were proposed and verified. Thefollowing is the main innovations and results in this dissertation.1. Based on Kirk effect and the amplification of the parasitic NPN structure, thenon-uniform conducting characteristic in width direction is studied. Then, a model of itis proposed. It can lead to low ESD robustness due to partial device conducting.According to the non-uniform conducting model, a device with high drain ballastresistance is proposed and verified. By splitting the drain N+region with field oxide, itshigh drain ballast resistance can suppress its non-uniform conducting and improve itsESD robustness without increasing the trigger voltage. Its failure current is increasedfrom1.06to3.53A.2. Based on Kirk effect, the holding voltage of the LDMOS is studied. The lowholding voltage is caused by the Kirk effect under ESD stress. According to it, a novelstrong snapback prevented LDMOS with high holding voltage is proposed and verified.The doping concentration of the part of the drift region near the drain is increased byadding a high concentration Nwell used in the low voltage PMOS device. In the device with high doping concentration drift region, Kirk status needs higher current density.Then, its holding voltage can be increased. The holding voltage of the proposed deviceis increased from15V to29.8V. Besides, no obvious strong snapback is found. Inaddition, since the electron injection from the source to drain influence the holdingvoltage, the influences of the channel length, the resistance in the base region of theparasitic BJT structure, and the current amplification coefficient on the ESDcharacteristics are also studied. A TLP characteristic without snapback can also be gotby using the PLDMOS with low current amplification coefficient as an ESD protectiondevice.3. A novel NPN-LDMOS structure is proposed. Its characteristics under ESD stressare studied and verified. Compared with the conventional LDMOS, the novel differenceis the added low voltage Pwell in the drain region of the proposed device. Then, aparasitic NPN device is formed in drain region. Under ESD stress, the avalanchegeneration junction in the LDMOS is changed from N+/Ndrift to N+/Pwell, which canlead to higher impact ionization coefficient and more current uniformity. The test resultsshow that its failure current is increased from1A to3.2A at the cost of the holdingvoltage decreased by merely6V.4. A novel SCR structure is proposed and verified for the I/O pad in CMOS circuits.The SCR can be triggered not only by the avalanche breakdown in the embeddedMOSFET, but also by the parasitic capacitance in the power rails. The device with smallwidth can provide enough ESD protection for the I/O pad, because its robustness ismuch higher than the conventional MOSFET. Its failure current is1time higher than theconventional MOSFET under nearly the same area conditions. Besides, it can alsoprovide basic ESD protection for the power rails by the embedded MOSFET withoutmuch extra area.