Reserch And Design On 14 Bits 100MS/s Pipelined Analog To Digital Converter

With the rapid development of 5G communication,Internet of Things,consumer electronics and high performance radar,the performance requirements of analog-to-digital converter(ADC)for various electronic products are getting higher,which requires ADC to have high conversion rate and high output accuracy.The Pipelined ADC(P-ADC)has the characteristics of simple structure,reconfigurable,high conversion rate and high output precision.Therefore,the research of P-ADC is of great significance to the application of high-speed and high-precision analog-to-digital converters.Depending on describing the working principle of P-ADC and analyzing the system parameters,and under the guidance of the simulation of P-ADC system model,the core module of P-ADC,sampling and holding circuit and comparator,are designed and validated by applying the design concept of gm/id respectively.On this basis,the background digital correction algorithm is studied to improve the output accuracy of ADC,and the design of 14 bits 100MS/s Pipelined ADC is completed.In this dissatation,the design of single-core P-ADC is deeply studied.And the methods of P-ADC modeling,together with key technologies to improve performance of P-ADC,are discussed.The main contents of this dissatation are managed as follows:Firstly,this dissatation analyses the working principle of P-ADC,and briefly describes the system structure of traditional P-ADC.The traditional P-ADC could be divided into four different basic functional modules,and some core circuits of the vatal basic modules are analyzed carefully.On this basis,a series of important system design and circuit design parameters in P-ADC are proposed and discussed.Secondly,in this dissatation,the P-ADC is modeled and simulated in detail.On this basis,the performance analysis of the whole P-ADC is carried out.The results of performance analysis are used to guide the design of ADC in the subsequent circuit design.In this dissatation,a new modeling method of sample-and-hold circuit is proposed.The second-order signal response model of OTA is improved and optimized to match the actual structure characteristics of sample-and-hold circuit.In the following chapters,the sample-and-hold circuit is designed and validated under the guidance of the simulation results.In addition,the main disturbances in ADC system are modeled and their effects are analyzed in detail.Through the complete performance analysis and Simulation of ADC system,system modeling and simulation provide good guidance and support for the decomposition of ADC system design parameters and circuit structure design.Thirdly,the sampling and holding circuit of P-ADC is designed and verified.According to the results of modeling and Simulation of Pipelined ADC system,the critical design parameters of sample-and-hold circuit are extracted,and a new model design scheme is proposed by applying advanced gm/id design idea.The design idea of gm/id is based on EKV model.Using gm/id as a unified design method can not only greatly improve the design efficiency,but also optimize the design results of the circuit because of its unification.Although this design concept has been put forward for some time,no complete design scheme has been put forward.In this paper,a design scheme of gm/id based on circuit structure modeling is proposed,and the automation design of OTA in ADC is carried out.The whole sample-and-hold circuit is designed and implemented based on TSMC0.18 mm CMOS process.The test results show that the gm/id design method is reliable and effective.Moreover,in this dissatation,the comparator in P-ADC is designed and verified.In this dissatation,a new method of optimizing high-speed and high-precision comparator is proposed.By modeling the signal response process of the comparator,the optimum circuit parameters of the comparator are selected by mathematical method.The comparator circuit is designed and implemented based on TSMC 0.18mm CMOS process,and the chip has been taped out.The test results show that when the system clock is 500 MHz,the response time of comparison is 380 ps,and the input offset voltage is 4 m V.At last,Aiming at the non-linear problem caused by system error in P-ADC,this dissatation studies the background calibration technology against gain error,and realizes a Harmonic Distribution Calibration(HDC)algorithm for harmonic distortion.For high-speed and high-precision ADC,the harmonic distortion caused by capacitor mismatch lay a great impact on the performance of ADC system,so it is necessary to calibrate the ADC system.The calibration technology is mainly divided into foreground calibration and background calibration.HDC background digital correction technology has the characteristics of not affecting the work of ADC system.By injecting random sequences into ADC,processing random sequences all through ADC system and due to the statistical characteristics of random signal,the high-order harmonic parameters caused by errors can be calculated and eliminated to correct the gain error.Background digital calibration algorithm obsecces better real-time performance.When the environmental parameters and circuit parameters change,it can adjust the calibration parameters in real time.It has high practicability.Moreover,the background digital correction is completely realized by digital circuit,which is the main research direction of the current correction algorithm.On the basis of ADC system modeling,this dissatation completes the design and verification of the vital ADC circuit modules,sample-and-hold circuit module and high-speed and high-precision comparator circuit module,and then studies the background digital correction algorithm of ADC circuit.Finally,the complete chip design of 14 bit 100MS/s Pipelined ADC is completed,The whole chip is based on TSMC 0.18mm CMOS technology.The simulation results show that with 10 MHz input sinusoidal signal,the ENOB of output is13.7bits at 100 MHz system clock.The designed chip has been taped out,and tested.According to the test result,power consumption of the chip is 214 m W with 1.8V power supply.With 10 MHZ input,SNDR of ADC is69.896 d B,ENOB is 11.3 bits.