An all digital high speed serial data transmisison/recovery system

Until recently, most high speed data communication systems employed phase-locked loops (PLL) for clock multiplication and clock extraction/retiming. Problems associated with traditional analog-based PLL designs and the difficulties encountered in monolithic implementation using a standard digital CMOS process, have prevented PLL designs from being integrated with VLSI digital CMOS products at high data rates. Various digital clock/data recovery systems have been developed to address this problem, including approaches employing calibrated delay line techniques. These digital approaches are either partially analog or effective only for a certain data or coding format. Generally, the approaches can be categorized into either synchronous sampling or uniform sampling.; An all digital clock multiplication/data recovery system, which is capable of transmitting data over high speed serial communication links and recovering any arbitrary binary sequence, and which can be implemented in digital CMOS has been developed and described in this dissertation. The architecture is based on a new and unique synchronous uniform sampling algorithmic technique using calibrated delay time ruler elements for bit serialization at the transmitter and for sampling clock synchronization with data at the receiver. Digital code controlled delay elements, each of which provides a calibrated delay equal to half of the bit period, are defined as the time ruler. The time rulers representing the multiplied target frequency at n{dollar}sp*{dollar}f obtained from matched delay elements are calibrated on-the-fly from a local reference source with a frequency of f. The time ruler elements are used both for generating the bit clock, and for providing a uniform bit interval for sampling the data to capture the distributed edge positions due to timing jitter. The sampling clock is a phase-shifted signal from the locally generated bit clock and must be constantly phase aligned with the average data transition position. The phase shifting is a function of time and a function of the frequency offset between the local clock and data. This alignment is achieved by detecting and averaging the captured data edge positions and subsequently processing the information to provide control signals for a digital phase adjuster to make proper phase adjustment. Unlike the PLL-based systems in which the performance relies on the data transition density, long data run length tolerance can be achieved with this system since the phase adjuster can be virtually "frozen" in the absence of data transitions. The system has demonstrated very satisfactory performance for the first wafer tested.