Design And Verification Of Network Chip Physicial Coding Sublayer Critical Circuits

With the rapid development of Internet technology, human life is more and more inseparable from the network. Services and other relevant areas of life, all the time between transmission of information should be carried out. And the network chip, which has been playing an important role. Currently, research on network chip, because code and checkout is the guarantee of reliable data communication, the coding and checkout efficiency is to determine the important factors of chip area. Therefore, the studing of the network chip physical coding sublayer is more and more important. As a result, this paper is based on a kind of network chip-fibre channel switch chip physical coding sublayer research, based on the advantages of fibre channel technology, and using the So C design flow, completing the design and verification of the physical coding sublayer critical circuits, and implements the design of reusable IP. In this thesis, the main work includes:1. At the beginning of the design, depth study of the relevant basic theories including physical layer structure and fibre channel technology. Based on thorough understanding of fibre channel protocol and physical coding sublayer, code and checkout algorithm of the chip physical coding sublayer is studied. Taking all factors, I obtained for fibre channel switch chip coding technology and checkout algorithm.2. Based on fibre channel protocol, and using the So C design flow, analysised of the architecture of fibre channel switch chip, and proposed a fibre channel switch chip PCS circuits functional properties. According to the specific functions of PCS module, put forward a design scheme of PCS module, and from the sending and receiving of two parts of the design details of each sub-module. Transmitting part of the design, realized the 8B/10 B encoder, the transmit buffer, and pseudo-random code generator design. Receiving part of the design, realized the 8B/10 B decoder, the receive elastic buffer, Comma testing and calibration, CRC check and other sub-modules design. Finally I realized the design of PCS module. And based on the research of fibre channel switch chip, this thesis presents the design of a reusable PCS critical circuits.3. After the design is completed, launch module-level simulation and system-level verification and FPGA implementation of PCS critical circuits. During the process of module-level simulation, firstly, according to the requirements of specification, functional specification and other written verification specification, preparation of test items; Then, according to the validation plan, write test cases, the module is verified. During the system-level verification, by adding different bus functional model, constituting the minimum virtual system required to switch chip woking. Then on other switch chip peripheral interfaces, by writing the corresponding test model, analog input and output operation of the peripherals, complete the simulation in virtual verification environment. FPGA implementation, mainly through comprehensive optimization of its resources and power were analyzed. Finally realized the simulation and verification of PCS critical circuit.