The EDA Applications Of Timing Analysis Considering Crosstalk For Digital Circuits

With the continuous development of integrated circuit technology, the ratio ofheight to width is increasing, which causes that the crosstalk effects generated bycoupling capacitance between adjacent signal lines is becoming more and moreserious in a circuit. Especially for the crosstalk-induced delay problem, a design can’twork in a normal clock cycle when the problem is severe. Timing analysisconsidering crosstalk is to more accurately predict the delay after placement androuting for a design according to the coupling capacitances, which can effectivelyguide the design and modification of the physical design. Timing analysis includesfast static timing analysis and slow pattern-based simulation, i.e. dynamic timinganalysis. Static timing analysis is based on the topology of a circuit. This methodcalculates the delay through static ways directly. It is very effective especially forlarge-scale circuits. Therefore, it is generally used in the design process as an essentialstep.Based on the research of crosstalk, we integrated the methods of static timinganalysis considering crosstalk into ICExplorer, an EDA tool of Huada EmpyreanSoftware. The applications of the two static timing analysis methods based on thetime window and transition map respectively, have been implemented. In terms ofdynamic timing analysis, the experiment circuit was simulated using HSPICE. Themain work of this thesis includes the following:1. The concepts of crosstalk effects and related analysis methods are introduced,which include crosstalk models, crosstalk effects, calculation of crosstalk delay andselection of target crosstalk faults.2. The static timing analysis methods are surveyed. Both traditional timinganalysis method and static timing analysis considering crosstalk are included. Thelater is based on timing window and transition map. Static timing analysis processconsidering crosstalk is also described.3. The dynamic timing analysis methods are surveyed, including the conceptsand classifications of paths, delay fault model, delay test path selection and testgeneration, dynamic simulation using EDA tools.4. The most important contribution of this thesis is the implementation of statictiming analysis considering crosstalk based on both timing window and transition map to an STA tool in a commercial EDA software. We introduced the STA tool, thesetting up experimental platform, the system processes, the specific realization ofstatic and dynamic timing analysis, and the experimental validation in detail.Finally, experimental results for the commercial circuit showed that crosstalkdoes affect the path delay. The method based on transition map is more precise torepresent the transition time of signal lines. It deletes more false crosstalk fault andthe analysis on crosstalk effect is also more accurate comparing to that of timingwindow based, but consumes more time and space.