Timing-oriented approach for delay testing and dynamic timing analysis

As VLSI fabrication process continues to advance and device and interconnect dimensions approach nano-scale, limitations of the fabrication process cause larger percentage variations and higher incidences of small defects. In turn, these alter delays of gates and wires. While the change in the delay value of a particular gate or wire may be small, changes in delay values of multiple gates and wires along some circuit path may cause that path's delay to exceed the desired clock period. Hence, it is increasingly important to test circuits for delay faults.;Once a minimum set of paths are identified, an automatic test pattern generator (ATPG) can be used in conjunction with these paths to obtain vectors that are able to excite the delay equal (or close to) the worst-case circuit delay. Current test generation algorithms need to generate a large number of tests to obtain a test that can excite the delay close or equal to the worst-case circuit delay. Developing a timing-oriented ATPG that can exploit both necessary logic and timing conditions for cost-effective pruning of targets, reducing ATPG complexity, and generating high quality tests is becoming important.;The goal of this research is to develop new methodologies and techniques for timing-oriented approaches for delay testing and dynamic timing analysis. We first develop the concepts of settling times and timing threshold to identify a minimum set of paths to be tested. We then identify properties of different types of paths as well as logic and timing conditions that are necessary to cover a target path and develop a new logic-and-timing implication procedure to exploit these conditions. We incorporate newly developed concepts in a new ATPG that also prioritizes the order in which these conditions are used to generate high quality vectors. We use this ATPG to identify paths that cannot or need not be tested and to generate high quality vectors for all other paths. Several applications are implemented, and the experimental results demonstrate the benefit of exploiting proposed concepts.;While a robust test that satisfies the classical definition guarantees propagation of a transition along the entire target path, detailed circuit simulations have demonstrated that a classical two-pattern robust test for a path delay fault may not excite the worst case delay of the target path. Since the purpose of our framework is to accurately estimate the bounds of the worst-case circuit delay, it is important to identify a minimum set of the paths that are able to excite the delay equal or close to the worst-case circuit delay.