| This thesis presents a new technology called Symbolic Timing Simulation (STS), and applies it to the timing and functional verification of full-custom transistor-level circuits.; Current methodologies verify functionality and timing separately to enable higher efficiency and capacity. However, for many full-custom circuits, timing and functionality are tightly coupled, rendering current methods ineffective. The lack of functional information during timing analysis implies that heuristics must be used to determine timing constraints such as latch setups, pulse-width constraints, etc. These heuristics are often unable to handle the range of possible design styles used in full-custom methodologies. Conversely, the lack of timing information can easily cause false failures during functional verification.; Our approach is a generalization of symbolic simulation, where Boolean variables are applied to the circuit inputs rather than constant 0's or 1's. In this manner, we effectively perform a timing simulation for every possible input pattern concurrently. By verifying that the resultant Boolean functions on the output nodes are correct, we can show that all internal timing constraints must have been satisfied without using heuristics to explicitly identify them. In addition, the functionality of the circuit is verified under the constraints of a realistic delay model.; While this methodology is substantially more compute-intensive than static timing analysis, it is surprisingly efficient and can be applied to a much more general class of circuits. To offset capacity limitations, we also present a methodology for extracting block-level timing models, so that STS may be used only where necessary, and its results used in higher-level static analyses. |
