| The goal of this research is to study the advanced architectures of data converters used in modern digital-signal-processing systems. This dissertation is separated into two parts: the first part presents my invention on high speed analog to digital converters (ADCs), and the second part focuses on high speed interpolators and interpolating digital-to-analog converters (DACs).; In the first part, I will present a new type of analog-to-digital converter (ADC) called floating analog-to-digital converter (FADC). The new FADC has the following advantages over existing designs, simple architecture, small size, low power dissipation, high speed, and adaptive time sampling interval characteristics. The high speed FADC can replace all existing high speed ADCs, such as folding, interpolating, pipeline and multistep ADCs. I designed and fabricated 6-bit, 8-bit, 10-bit and 12-bit FADCs. The experimental results indicated the FADCs have very good characteristics. The sampling speeds of 6-bit, 8-bit, 10-bit and 12-bit FADCs reach 800, 650, 150 and 80Ms/s respectively. These speeds are about three times faster than the other reported CMOS mutlistep, folding and interpolating ADCs in the journals. Moreover, the FADCs have the lowest reported power dissipation of 50, 60, 50 and 110mWatts for 6-bit, 8-bit, 10-bit and 12-bit at 5v respectively. The die sizes of the FADCs are 0.2, 0.35, 0.3 and 0.5 mm2 respectively, which are approximately ten times smaller than the other ADCs. The test chips are manufactured by a double poly treble metal 0.6mum CMOS technology. The new FADC can be implemented as two or multi-steps structure. The unique structure of the FADC makes it suitable for automatic design tool such as VHDL.; The second part of my dissertation is focused on DAC designs using interpolation technique. I will present sinc interpolation theory and technology, derive the limited-time sampling and reconstructing theorems as well as interpolating equations. I have deigned three sinc function (2X, 4X and 8X) interpolators with a single poly double metal 0.8mum CMOS technology. The speeds of 2X, 4X and 8X sinc interpolators are 50MHz, 40MHz and 30MHz respectively. The size of a 2X sinc interpolator is 3 x 2.5 mm2. The power dissipation of the test chip is 80mwatts at 50MHz and 5V supply. Besides the sinc interpolator, I have also developed the 16X linear interpolating and curve interpolating DACs to increase the sampling rate. The linear and curve interpolating DACs (LIDAC and CIDAC) can operate as high as 500MHz. The measurement results indicated that the LIDAC and CIDAC can indeed ease the requirements of ADC and DSP. I used a CMOS single poly double mental 0.8mum CMOS process to manufacture the chip. The test chip size is 2.4 x 2.4 mm2. The power supply is 5v and the power dissipation is 60mwatts. The SNDRs of the linear and curve interpolating DACs are 68dB and 69dB respectively, which is about 18 dB better than an R-2R DAC (51 dB measured SNDR) operating under the same condition. |
