Test strategies for built-in self-test at the algorithmic and register-transfer levels

Design-for-test (DFT) methods for application-specific integrated circuits are presented. The methods are based on pseudorandom built-in self-test and target three constructs that can cause testability problems. These problems are examined and test strategies to overcome these problems are proposed. Testability is considered at the algorithmic and register-transfer levels of circuit design.; The first construct is reconvergent fanout in the algorithmic description of the circuit behavior. Reconvergent fanout occurs when the inputs to one operation both depend on the output of another operation. These inputs are correlated, which can restrict test patterns and mask defects. The correlation metric identifies correlated variables.; Control statements, which are conditional and loop statements in the circuit behavior, make up the second construct. Testability is complicated for several reasons. Control statements decide the path exercised in the behavior, and test patterns for the conditional branches can be restricted. Metrics identify these problems. Fault detection through the relational operations of control statements is poor.; The third construct involves random-pattern resistance. Pseudorandom techniques use random patterns to test the modules in a circuit. However, some modules need specific test patterns or patterns with a particular characteristic in order to be tested effectively.; Most of the test strategies are implemented by modifying the status and control signals between the datapath and controller. To test relational operations, they are bound to subtraction operations in the datapath. To test random-pattern-resistant modules, the controller is modified, and the datapath may be modified. The DFT methods do not impose design restrictions and can be applied either during or after high-level synthesis.; Experimental results from seven example circuits show that the DFT methods are effective. The hardware area and critical delay overheads were usually less than 5%. Fault coverage improved when the circuits were modified using the proposed test strategies. Nearly all datapath faults in the modified circuits were detected, and for most of the examples, controller fault coverage improved as well. The goal was to improve datapath fault coverage, and testability of the controller was not considered.