Extending the reach of self-test approaches in VLSI

Design for test methodologies, including built-in self-test (BIST), play a significant role in managing the test cost of current designs. While BIST provides a significant cost reduction in test generation and test application, fault coverage levels and diagnostic capabilities are deteriorated due to random resistant faults and limited response information, respectively. In addition to benefits in manufacturing testing, BIST can be utilized to provide fault tolerance when executed concurrently with the original functionality. However, in the case of concurrent testing, attaining high fault coverage levels with no advance knowledge of the inputs usually necessitates high area overhead.; Initially, an extensive study of on-chip pseudo-random test pattern generators is performed and methodologies for selection of suitable pattern generators for VLSI designs are investigated. After disproving the claims that randomness plays an important role in ascertaining the quality of pattern generators, methodologies for reducing the cost of deterministic test pattern application are investigated. The compression scheme proposed in this work, together with an on-chip decompression hardware, provides significant reductions in test application cost.; On the fault diagnosis side of testing, efficient fault diagnosis approaches are proposed for scan-based BIST designs. Improvements in information extraction from BIST signature are attained through utilization of both superior deterministic partitioning schemes and enhanced analysis procedures. Gate-level fault diagnosis is achieved through utilization of set operation-based pruning algorithms on small fault dictionaries. The diagnosis scheme proposed in this work provides one of the first results for automated gate-level fault diagnosis of BIST designs.; Finally, investigation of concurrent test for linear digital systems provides a low cost, accumulation-based concurrent error detection scheme. The success of the proposed scheme stems from both observation of the average behavior of the linear systems, as opposed to the instantaneous behavior observation of the previous work, and careful gate level fault effect analysis and circuit modifications to guarantee complete fault coverage.; Prototype implementations of all the proposed methods in this work are developed and experimental results attained through computer simulations. Results of analysis and experiments performed in this work provide solid evidence that this work achieves significant advances in BIST technology so as to extend its applicability to a broader design domain.