Low-power low-jitter on-chip clock generation

Phase locked-loops (PLLs) are widely used to generate well-timed on-chip clocks in high-performance digital systems. Any timing jitter or phase noise significantly degrades the performance of these systems, especially as operating frequency increases. Switching activity in large digital systems introduces power supply or substrate noise which perturb the more sensitive blocks in a PLL, in particular, voltage-controlled oscillators (VCOs) and clock buffers.; Power dissipated by PLLs is often a small fraction of total active power. However, during sleep modes where the PLL must remain in lock, it can be a significant fraction of dissipated power. Also, for some applications such as high speed parallel links and distributed synchronous clocking, multiple PLLs are employed to minimize the timing uncertainty. Therefore, demand for low-power PLLs has been increasing. The low-power requirement makes the design of a low jitter PLL even more challenging.; This research describes the design of a fully-integrated low jitter PLL for low-power applications. To achieve the low jitter performance, this work proposes jitter minimization methods at both system and circuit levels.; At the system level, this work investigates the effects of PLL design parameters, such as bandwidth and peaking in the frequency response, on timing jitter of PLL output clock. The analysis includes several common noise sources in a PLL and develops an intuition for selecting design parameters to obtain minimum output jitter based on the dominant noise source. The proposed PLL is equipped with digitally-controllable loop parameters that independently adjusts the loop parameters. Based on jitter analysis, a methodology for on-chip adaptive jitter minimization in PLLs is developed. The proposed method measures the output jitter and adjusts the PLL loop parameters toward minimizing the jitter by a closed loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5ps of the minimum long-term peak-to-peak jitter.; At the circuit level, two new supply rejection techniques for VCOs and clock buffers are developed. Both methods demonstrate the delay sensitivity of ≤0.1%-delay/%-VDD due to both static and dynamic supply noise. While the jitter performance is comparable with prior state-of-art work, the proposed VCO and clock buffer consume less power with smaller area than previous designs. The VCO is designed to operate over a wide frequency range and has a linear voltage-to-frequency gain. The PLL is designed with scaling loop parameters that track over a 10x frequency range of the VCO and allow the adaptive loop bandwidth. The PLL is implemented in 0.25-mum CMOS technology and consumes 10mW from a 2.5-V supply.