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Keyword [Plls]
Result: 1 - 13 | Page: 1 of 1
1.
The Research And Design Of Low Jitter Plls With Wide Frequency Range
2.
Design And Implenmentation Of A 2.5Gbps CMOS Monolithic 16:1 Multiplexer
3.
Used In Uwb Systems, Low-power Frequency Synthesizer Design And Research
4.
The Research And Design Of Low Spur Low Jitter Phase Locked Loop In CMOS Process
5.
Research On Attenuators And Phase-Locked Loops For Silicon-Based Phased Array Systems
6.
Research On Extremely-Low Jitter Synthesizer Based On Dual Plls
7.
Low complexity delay and phase-locked loops
8.
Design techniques for PVT tolerant phase-locked loops
9.
Delta-Sigma FDC Based Fractional-N PLLs with Multi-Rate Quantizing Dynamic Element Matching
10.
Oscillation control in CMOS phase-locked loops
11.
Phase realignment and phase noise suppression in PLLs and DLLs
12.
Low-power low-jitter on-chip clock generation
13.
Timing jitter/phase noise in phase-locked loop modeling and multi-gigaHz PLLS design
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