Research On On-chip PLL Clock Generator For MAPS

This work is part of the MAPS R&D program at IPHC, Strasboug, France, dedicating to development of on-chip clock generation PLL in the sensors. MAPS are elementary device in high-energy physics experiment. Since 1999, IPHC initially proposing the idea of using MAPS devices for high-energy charged particle tracking, MAPS have demonstrated their strong potential for this application. New generation of will be integrated with functional modules, such as data compression circuitry, memory and serial link transimitter. All of these blocks require high quality clock. Any timing jitter on the clock will degenerate the performance of them. Therefore, the development of the on-chip PLL (Phase-Locked Loop) clock generator is a significant work.The thesis discusses the theory and implementation of integrated PLL clock generator, and research several techniques for optimizing PLL design and improving clock quality on a real chip.Power supply noise is a dominant noise contributor in a PLL clock generator. The thesis introduce the impact of power supply noise in a chip on PLL clock quality, then presents an on-chip voltage regulator which could relieve PLL power supply noise sensitivity. The on-chip voltage regulator employs two low dropout voltge linear regulator in serial connection to enhance its power supply noise immunity. Each of the linear regulators uses a technique named virtual ground cascode compensation which can improve power supply nosie rejection in high frequency. A prototype PLL was designed and fabricated in a 0.35 m CMOS technology. The measured circuit shows great power supply noise immunity.In a submicron or nanometer technology, power supply voltage is scaled down due to the limits of low power consumption requirement and breakdown voltage of devices. Since traditional voltage regulator have dropout voltage of several hundreds millivolt, it is a real challenge to design high performance analog circuits which are supplied by the regulator. The thesis proposes a on-chip voltage regulator which combines charge pump and linear regulator to generate on-chip power supply. The circuit can be used in a low power supply PLL. The propsed circuit was verified by simulation in a 0.13 m CMOS technology. One of the challenges in PLL integration is that the on-chip capacitors are to large to implement. The thesis introduces several techniques to solve the on-chip capacitors problem, including dual-path, impedance scaling, etc.. All of these schemes utilize additional active elements without exception, which inevitably contribute considerable active noise to PLL in-band noise. The thesis proposes an area-efficient, passive PLL loop filter. Though the loop filter decreases the size of on-chip capacitors by dual-path architecture, there are no additional noise and power consumption contributor due to the absence of active device. The thesis discusses linear model of a PLL based on the proposed loop filter. Compare with tradditonal loop filter shows the proposed scheme saves capacitor size up to 90%.