Timing jitter/phase noise in phase-locked loop modeling and multi-gigaHz PLLS design

Phase-Locked Loops (PLLs) are widely used as frequency synthesis, clock signal recovery, etc, in various communication systems. The increasing requirements of low timing jitter, low phase noise, high speed and wide range make the design of a PLL extremely difficult. The first part of this thesis gives a methodology for analyzing and predicting the timing jitter/phase noise of a PLL system. Theoretical models are derived in the different hierarchy levels in a PLL system. The theoretical models correlate the phase noise/timing jitter with the design parameters. The design implications for low phase noise/timing jitter are derived after each model. The second part of this thesis describes the circuit designs and the test results of the three fully integrated multi-GHz PLLs fabricated using deep sub-micron digital CMOS technologies. These include a 1.25GHz PLL designed in a NEC 0.24um, 2.5V CMOS technology, a 2GHz to 3.3GHz rate-agile PLL and a 600MHz to 3.3GHz PLL designed in TSMC 0.18um, 1.8V CMOS technologies. This later design represents the widest range PLL in the industry reported to date. These designs make use of the theoretical phase noise/timing jitter models developed in the first part to minimize the timing jitter and phase noise in PLLs. A dual-loop architecture is invented to reduce the phase noise/timing jitter and achieve a wide lock range at the same time. A new negative feedback scheme is also introduced to further extend the voltage-controlled oscillator range. The measurement results from the silicon have good agreements with the theoretic results developed in the first part of the thesis.