Design Of On-Chip Power Systerm For High Speed And Low Jitter Clock Circuit

With the progress of CMOS technology and the wide application of on-chip system chips(SoC),the traditional power management solutions cannot meet the demand of SoC for power supply.Some circuit blocks in SoC are sensitive to power supply noise and ripple.It is often necessary to integrate LDO into the chip to provide them with clean power supply voltage.Currently,designing LDO with low design cost,easy integration,no need for off-chip capacitors and high PSR is a challenge.The capacitor-less LDO is a hot research structure in recent years.It does not need off-chip capacitors and is suitable for integration into SoC.Therefore,this paper studies and designs a capacitor-less LDO,which can be integrated into the SoC.In this paper,the structure principle and design difficulties of LDO are deeply studied and analyzed.By analyzing the function and optional types of power MOSFET,the NMOS is used as power MOSFET of LDO.By analyzing the loop structure of LDO,Miller compensation and impedance attenuation are used to compensate the frequency of the loop,so that it can be stable in light and heavy loads.By analyzing the principle of PSR of LDO,this paper designs sufficient loop gain to ensure that the LDO has a better PSR in the low frequency band.In order to optimize the PSR in the middle frequency band near 1MHz,the feed-forward ripple cancellation technology is used and a special auxiliary circuit is designed to improve PSR of the circuit.To meet the demand of the LDO for bias voltage,a bandgap reference circuit with high PSR and low temperature coefficient is designed.In order to ensure the power supply safety of the whole system chip,an over-current protection circuit is designed.In addition,the layout design of the circuit and the simulation verification of the parameter performance are also carried out in this paper.Based on 40 nm CMOS technology,a LDO is designed to supply power to digital circuits and clock circuits in high-speed and high-precision ADC.The Hspice software is used to simulate the performance of the circuit.The simulation results show that the input voltage of LDO is 1.9 V and output voltage is 1.3 V.Within the load current range of 100 ?A to 50 mA,the circuit has good loop stability and load regulation.Its phase margin is above 60 degrees,and the static fluctuation of the output voltage is less than 100 ?V.The PSR reaches-69.8 dB in low frequency band,and-27.7 dB at 1MHz.In addition,the regulator has reliable over-current protection function.