A differential-based multiple bit rate PSK receiver: Theory, architecture, and SOI CMOS implementation

The development of telecommunications electronics with low power and low mass will be significant for future deep-space communications. The design of a receiver for deep-space communication requires the receiver to be robust against frequency variations due to Doppler effect in addition to radiation tolerance and low-power consumption. This dissertation reports a very low-power differential-based phase-shift keying (PSK) receiver that is targeted at deep space and satellite communications, on both architectural and implementation levels. The power consumption of the PSK baseband circuit alone is less than 100 muW, which is significantly better than previously reported designs. Another major feature that has not been previously offered for PSK modulation is the use of 1-bit analog-to-digital converter (ADC) with sub-sampling front-end.; The receiver uses double differential detection with traditional PSK modulation in the baseband to eliminate the impact of Doppler shift. Furthermore, the baseband can be employed in IF-sampling and sub-sampling front-end. Both front-ends offer minimal power consumption and differ from many traditional ones by eliminating some existing problems such as DC offset, dc voltage drifts and 1/f noise. The receiver also incorporates digital decimation stages to accommodate variable bit rates, and therefore it is highly programmable. The ability to support a wide range of data rates is an important feature of the receiver. This is achieved via digital channel selection by means of digital signal processing (DSP). A timing circuit robust to Doppler shift is also introduced for the proposed PSK receiver. Unlike conventional timing circuits, the proposed circuit consists of a 1-bit ADC at the front to convert analog signal to digital signal and a pre-filter to eliminate frequency error due to Doppler. In addition, the circuit is designed for multiple bit rates. The worst-case observed timing offset from the implementation for all data rates is less than 1/10 of the symbol period of the highest bit rate 100 Kbps (i.e. Delta Tmax = 1 mus).; The baseband and an analog part of the receiver are realized in 0.35 mum Silicon-on-Insulator (SOI) CMOS. SOI Complementary Metal Oxide Semiconductor (CMOS) technology is used mainly because it is a radiation hardness process. SOI technology is currently the most attractive choice in transceiver designs due to its advantages in both speed and power over standard CMOS because of lower parasitic capacitances. The designed baseband circuit consumes a power as low as 90.6 muW from a 1.1 V power supply. (Abstract shortened by UMI.)...