| This thesis focuses on CMOS wireless receiver design. (1) At RF region, the impact on MOS transistor, inductor and capacitor was investigated. (2) Active Q-enhanced techniques are reviewed. A new passive technique to enhance the LNA's Q factor is introduced. The approach makes use of three RLC 2nd-order band-pass (BP) circuits that are tuned to the same frequency in order to enhance the global Q without the need for any active or positive feedback compensation. It shows Q of 37 can be obtained while only 5.6 mW power consumption is drawn from a 1.5 V do supply. (3) A novel adaptive gain CMOS RF front end receiver is proposed. The new receiver enlarges the dynamic range 13 dBm of the received signals. It includes a variable gain low noise amplifier (LNA), double-balanced mixer, low-pass filter, automatic gain controller (AGC) and variable gain amplifier (VGA). The LNA's frequency locations at the maximum gain and at the minimum S11 and S22 are kept nearly unchanged even though the gain is varied. (4) Four different receiver architectures are reviewed. Block IF conversion architecture is suggested. System level analysis and simulation of band-pass delta-sigma modulator is introduced. Circuit implementation of high frequency tunable band-pass Gm-C loop filter is presented. (5) Circuit layout and package issues are analyzed. Physical layout of an adaptive gain front end receiver is presented. |
