Design And Study Of Low Power Consumption And High Performance CMOS Domino Circuit For32nm-node Technology

For the past few years domino dynamic circuit draws the widest attentions because of itshigh speed and small area of back-end layout compared with static CMOS circuits. Thus it iswidely applied in the critical path of high performance ICs. Yet domino circuit powerconsumption become larger and larger as the feature size of domino circuits. CMOS circuitpower consumption contains dynamic power and leakage current power which shall be one offocuses during the integration circuits design.Single transistors with different process sizes (32nm,45nm,65nm) are compared basedon32nm CMOS BSIM4model and the leakage current variation with the decrease of theprocess size is presented by H-spice stimulation. The32nm CMOS Domino basic logic unitsare designed and optimized. The optimization steps include:(1) adding source-followstructure to enlarge the circuit noise tolerance of p-type Domino OR gate by66%;(2) usingP-N mixed pull-down network technology to reduce both dynamic and minimum static powerconsumption by19%and80%respectively. Then some complex logic units are designed inform of Zipper on the base of32nm CMOS domino basic logic units. Circuit optimizationsare made by the double threshold voltage technology and charge self-compensationtechnology. The results shows that the minimum static power consumption of Parity Checkcircuit is lowered by62%after introducing double threshold voltage technology and thedynamic and static power of the new Digital Comparator were reduced by25%and42%respectively after using charge self-compensation technology.