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A 900-MHz low-power CMOS receiver for wireless integrated network sensors

Posted on:2002-06-01Degree:Ph.DType:Dissertation
University:University of California, Los AngelesCandidate:Lin, Tsung-HsienFull Text:PDF
GTID:1468390011998652Subject:Engineering
Abstract/Summary:
Wireless Integrated Network Sensors (WINS) has been proposed for various applications. It consists of many smart nodes to perform co-operative detection. The remote sensing nodes are battery-powered and the stringent power limitation poses great challenges in transceiver design. In order to achieve optimal performance at low power, a multi-hop networking scheme is proposed and the link budget characteristics of short RF communication is examined. Furthermore, frequency-hopped spread spectrum technique is adopted in the system to avoid issues of interference.; This dissertation presents a low-power CMOS receiver designed for WINS applications. The receiver path implementation exploits systematic link budget advantage to prevent over-specifications. Furthermore, by virtual of high-Q passive integration, key RF building blocks achieve high performance at low power.; The low-power frequency synthesizer is designed as an integer-N PLL with an LC-VCO. This PLL incorporates binary-weighted switched-capacitor arrays to facilitate VCO's tuning. This is implemented by adding an auxiliary SC tuning loop to the main synthesizer loop. With this technique, the VCO gain (KVCO) can be kept low to improve the PLL phase noise and spur performance, while the overall frequency tuning range is stiff wide. More important, this approach does not raise the total current consumption since the added circuitry can be powered-down once the calibration is complete.; The WINS receiver is designed to operate at the 900 MHz ISM band. Implemented in a 0.6-μm CMOS process, the receiver achieves 45 dB gain, 20 dB NF, IIP3 of −11 dBm, and IIP2 of +12 dBm. The measured VCO phase noise at 100 kHz offset is −100 dBc/Hz and the PLL reference spurs are below −50 dBc. Including the VCO and PLL, the complete receiver dissipates 6.1 mA from a 3-V supply.; Finally, an integration approach combines the elements of high-Q off-chip passive components, chip carriers, and PCB is proposed. It is based on the LTCC technology. Several VCO circuits has been implemented in LTCC and they have demonstrated the feasibility of this integration scheme.
Keywords/Search Tags:VCO, Receiver, CMOS, WINS, PLL, Low-power
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