A low power CMOS receiver for GPS application

The growing Global Positioning System (GPS) market demands lower power and lower cost solutions for integrated receivers while the trend towards ultra-miniaturization requires the use of fewer, if any, external components. A fully-integrated quadrature low-IF Li-band GPS receiver consuming only 6.4mW in 0.13mum CMOS is presented in this work.An energy-efficient RF front-end merges low noise amplifier (LNA), quadrature mixer, and quadrature voltage controlled oscillator (VCO) with current-reuse topology in a single stage. The structure, called the quadrature LMV (QLMV) cell, performs RF amplification, mixing, and quadrature phase local oscillator (LO) generation while sharing the same bias current and the same devices among all the blocks of the RF front-end, resulting in a very low-power, small-area solution. A new coupled scheme of quadrature VCO is proposed with low phase noise and accurate quadrature phase generation. With the proposed gate-modulated quadrature VCO, it succeeds to merge with RF front-end in a current-reuse stacked topology that consumes only 1mW. In addition, all local frequencies required for the receiver are generated from a highly-integrated power-optimized phase-locked loop (PLL).A high dynamic range continuous-time quadrature bandpass Sigma-Delta analog-to-digital converter (ADC) is imbedded in a low-IF architecture. The second order SigmaDelta ADC uses continuous-time circuitry, and thus has inherent anti-aliasing filtering properties. This allows simplification of the overall system and avoids noise folding which suffers from switched-capacitor circuits. With the inherent filter characteristic of the continuous time Sigma-Delta ADC, the data converter plays double roles of IF signals filtering and digitizing. In addition, the quadrature bandpass modulator outperforms bandpass and lowpass counterparts in power efficiency. Further power saving is achieved with the resistor feedback implementation instead of power hungry current steering DAC.This work has been implemented in IBM 0.13 mum CMOS process. The RF front-end has conversion gain of 42.5 dB, and the Sigma-Delta modulator shows dynamic range (DR) of 65 dB. The PLL phase noise at 1M Hz frequency offset is -110dBc/Hz, with quadrature phase error less than 1°. The receiver NF is 6.5 dB, while the total power dissipation of the GPS receiver is only 6.4mW.