Design Of Monolithic Photodetector And Amplifying Circuit Based On CMOS Process

In recent years,with the rapid development of optical interconnection and optical communication,monolithic optoelectronic integrated circuit(OEIC)optical receiver with low cost,high performance and CMOS-process-compatible has become a research hotspot.Because the photodetector and the preamplifier determine the performance of the OEIC optical receiver,this thesis makes a thorough research on the photodetector and the preamplifier under the standard CMOS technology,and the following work has been carried out:In order to improve the transmission rate of the OEIC optical receiver,a high speed photodetector compatible with the 0.18?m CMOS process of a domestic foundry is designed in this thesis,and the contrastive simulations of the structures on the high speed photodetector and double photodetector were carried out by Atlas software.The simulation results show that the photocurrent,responsivity and quantum efficiency of the high speed photodetector are larger than the double photodetector's,but the bandwidth of the high speed photodetector is less than the double photodetector's.The responsivity of the high speed photodetector for 850 nm is 0.077A/W,the parasitic capacitance is 1.16 pF,and-3dB bandwidth is 538 MHz at 5V reverse bias.The high speed photodetector was tested after taped out,the test results show that the responsivity is 0.0545A/W and the parasitic capacitance is 2.97 pF for 850 nm at 5V reverse bias.Although the bandwidth of the high speed photodetector is large,the responsivity is small,which limits the sensitivity of the OEIC optical receiver.In order to improve the responsivity of photodetector,a high responsivity PIN photodetector based on the 0.35?m CMOS process of a foreign foundry is designed in this thesis.Atlas software is used to simulate the influence of the intrinsic layer concentration and thickness on the PIN photodetector.Atlas simulation shows that when the operating voltage and the thickness of the intrinsic layer are fixed,there is an optimal intrinsic layer concentration,which makes a good tradeoff between responsivity and bandwidth of PIN photodetector.The thicker the intrinsic layer of the PIN photodetector,the larger the responsivity of the PIN photodetector,but the smaller the bandwidth of the PIN photodetector.Then,the device model of the PIN photodetector provided by the foreign foundry is simulated by Cadence software.And the PIN photodetector was tested after taped out.Cadence simulation shows that the responsivities of two PIN photodetectors with an area of 443?m×443?m and an area of 1500?m×800?m are 0.28A/W for 905 nm at 5V reverse bias.As the reverse bias increases from 0.5V to 5V,the parasitic capacitance of PIN photodetector with an area of 443?m×443?m decreases from 4.71 pF to 3.15 pF.And the parasitic capacitance of PIN photodetector with an area of 1500?m×800?m decreases from 22.8pF to 17.1pF.The test results show that the responsivities of the two PIN photodetectors are about 0.28A/W for 905 nm at 5V reverse bias,these are in good agreement with the simulation results,but the parasitic capacitances of the two PIN photodetectors are obviously larger than the simulation results.Finally,this thesis improves the conventional RGC input stage by using auxiliary amplifier technology.It improves the feedback path gain of the RGC input stage,thereby reducing the input resistance of the RGC input stage,and improving the bandwidth of the RGC input stage.single stage push pull structure is used for the post stage transimpedance amplifier.The output stage adopts the source follower structure.Cadence simulation shows that the resistance gain of the RGC transimpedance amplifier is 89.3dB?,and the-3d B bandwidth is 83 MHz.The output swing is 77 m V,and the rise time and fall time of the output voltage is 4.48 nS and 4.54 nS respectively.The RGC transimpedance amplifier can work normally at different process corners when temperature ranges from-40? to 50?.