| This thesis focuses on system level design strategies and techniques for circuit level implementations that facilitate low-power RFICs in bulk CMOS. Ultimately, the goal of this work is to enable the design of inexpensive and completely integrated circuits that consume so little power that they can be self-powered while communicating by means of an integrated antenna. As an application example, the design and implementation of a unique low-power integrated FM receiver is presented. The receiver is a completely new topology, using a modified PLL operated in both open-loop and closed-loop configurations, and using oscillator injection locking to accomplish FM demodulation with a minimum of circuitry. The receiver communicates at 5.2 GHz while consuming 285 muW when duty cycled in a typical application.;The appropriate background theory and calculations necessary to understand the design of the circuits are presented, along with the details of the circuits themselves and their simulated and measured behaviours. A brief discussion on the design and behaviour of the transmitter circuit is also included, as this discussion fosters understanding of the receiver design and the novel transceiver topology.;The receiver represents one half of a collaborative research project which developed a novel integrated transceiver suitable for short range wireless applications such as RFID tagging or the transmission of data from medical sensors. The circuit is unique in that it is virtually completely integrated, optionally making use of an on-chip antenna, and has such low power consumption that it could be self-powered by a thin film ultracapacitor and solar cell stacked on top of the chip. Both the transmitter and receiver consist of PLLs which initially phase lock VCOs, and then allow them to "roll" in order to transmit and receive the signal. The VCO in the receiver is injection locked by the incoming signal. The current design has a communication range of 6.5 cm when integrated antennas are used for both ends of the link, which can be increased at the expense of the data rate or increased power consumption in the receiver. When one end of the communication link uses a 6.7 dBi off-chip patch antenna, the communication range increases to 1.75 m. |
