| Clock and data recovery circuits (CDRs) have been widely used in data communication systems. This dissertation presents a half-rate clock and data recovery circuit that combines the best features, fast acquisition and low jitter, of digital phase selection and phase locked loop CDR circuits. This CDR circuit consists of a phase selector, which can lock to the data in just a few clock cycles but has high jitter, and a PLL, which requires a much longer acquisition time but provides a low jitter clock after locking. Measurements in 0.5 mum CMOS technology show operation up to 700 Mbps, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock in about 700 ns from an initial frequency difference of 7%.; A phase frequency magnitude detector (PFMD) is added to the combined CDR to improve the acquisition time by feeding back an estimate of the magnitude of the frequency offset in addition to the sign. Measurements show that the 700ns acquisition time is reduced by about a factor of 5 to 140ns from an initial 7% frequency difference.; This dissertation also presents an analog version of the PFMD CDR in the 0.25 mum CMOS technology without the entire overhead associated with the phase selector CDR in order to reduce power dissipation and area compared to the combined CDR. |
