| Continuing advance in CMOS technology has brought both opportunities and challenges to IC designers in nanometer-scale technology. Smaller transistor enables an increased level of integration, leading to a true system on-a-chip (SOC) where complex analog and digital circuits are integrated on the same substrate. While digital circuits greatly benefit from increasingly faster and cheaper digital gates, technology scaling gives much less appreciable benefit to analog circuits, posing a significant challenge to designing higher-performance yet lower-power analog and mixed-signal circuits in nanometer technology.;Among many paths to address the challenges in analog circuit design, this research work demonstrates a comprehensive design optimization that spans multiple levels of design hierarchy: device, circuit, and architecture. The design optimization framework consist of a pipelined ADC model and equation-based optimizer via geometric programming, a special kind of convex optimization. The ADC model captures intricate design tradeoffs in multiple levels of hierarchy, allowing circuit designers to quantitatively examine globally-optimal design tradeoffs between performance and cost, which is prohibitively complex to track in a traditional analog design flow.;A multi-level power optimization is proposed by taking advantage of the introduced optimization framework of pipelined ADC. In circuit-level, it is shown that the limited intrinsic gain of scaled CMOS device can be boosted by optimally selecting the device type among the multitude of devices offered in nanometer CMOS technology. In addition, simultaneous optimization of analog and digital supplies along with signal dynamic range helps achieve minimum combined power from analog and digital domain. In architecture-level, resolution and gain error across the pipeline stages are optimized to further reduce power dissipation. Proposed power optimizations are applied to designing a low-power 8-bit 320MS/s pipelined ADC in 90nm CMOS technology. Measured performance from the implemented prototype chip shows 254fJ/conversion-step energy efficiency with 7.30b of ENOB at Nyquist frequency. |
